1667 Commits

Author SHA1 Message Date
Matt Arsenault
19b50e8dff DAG: Add computeKnownBitsForFrameIndex
Some of the AMDGPU stack addressing modes require knowing the sign
bit is zero. We used to accomplish this by custom lowering
frame indexes, and then putting an AssertZext around a
TargetFrameIndex. This required specifically looking for
the AssextZext + frame index pattern which was moderately
disgusting. The same could probably be accomplished
with a target specific node, but would still
require special handling of frame indexes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317671 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08 08:52:31 +00:00
Simon Pilgrim
9fc9ff98ac [SelectionDAG] computeKnownBits - use ashrInPlace on known bits of ISD::SRA input. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317087 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-01 13:16:48 +00:00
Simon Pilgrim
84256dd936 Fix unused variable warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316964 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-30 22:38:07 +00:00
Simon Pilgrim
64ef8950b1 [SelectionDAG] Tidyup computeKnownBits extension/truncation cases. NFCI.
We don't need to extend/truncate the Known structure before calling computeKnownBits - it will reset at the start of the function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316962 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-30 22:23:57 +00:00
Simon Pilgrim
6d2ed8bccc [SelectionDAG] Add VSELECT demanded elts support to computeKnownBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316947 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-30 19:31:08 +00:00
Simon Pilgrim
d556da541d [SelectionDAG] Add VSELECT support to computeKnownBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316944 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-30 19:08:21 +00:00
Simon Pilgrim
d17a19ebd1 [SelectionDAG] Add SELECT demanded elts support to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316933 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-30 17:53:51 +00:00
Simon Pilgrim
63745a67d6 [SelectionDAG] Add SEXT/AND/XOR/Or demanded elts support to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316875 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-29 22:03:37 +00:00
Simon Pilgrim
b3d173b269 [SelectionDAG] Add SRA/SHL demanded elts support to ComputeNumSignBits
Introduce a isConstOrDemandedConstSplat helper function that can recognise a constant splat build vector for at least the demanded elts we care about.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316866 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-29 18:19:37 +00:00
Simon Pilgrim
1f5b3589c8 [SelectionDAG] Add support for INSERT_SUBVECTOR to computeKnownBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316847 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-28 22:10:40 +00:00
Simon Pilgrim
559a395253 [SelectionDAG] Support 'bit preserving' floating points bitcasts on computeKnownBits/ComputeNumSignBits
For cases where we know the floating point representations match the bitcasted integer equivalent, allow bitcasting to these types.

This is especially useful for the X86 floating point compare results which return all/zero bits but as a floating point type.

Differential Revision: https://reviews.llvm.org/D39289

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316831 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-28 14:27:53 +00:00
Sean Fertile
53b3cd421e Add subclass data to the FoldingSetNode for MemIntrinsicSDNodes.
Not having the subclass data on an MemIntrinsicSDNodes means it was possible
to try to fold 2 nodes with the same operands but differing MMO flags. This
would trip an assertion when trying to refine the alignment between the 2
MachineMemOperands.

Differential Revision: https://reviews.llvm.org/D38898

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316737 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-27 04:02:51 +00:00
Adrian Prantl
4a39ef301e Implement salavageDebugInfo functionality for SelectionDAG.
Similar to how llvm::salvagDebugInfo hooks into InstCombine, this adds
a hook that can be invoked before an SDNode that is associated with an
SDDbgValue is erased to capture the effect of the deleted node in a
DIExpression.

The motivating example is an SDDebugValue attached to an ADD operation
that gets folded into a LOAD+OFFSET operation.

rdar://problem/32121503

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316525 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24 22:55:12 +00:00
Adrian Prantl
5cb4d68851 Use range-based for loop. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316496 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24 20:38:00 +00:00
Simon Pilgrim
70d05d486e [SelectionDAG] Add VSELECT support to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316457 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24 16:38:38 +00:00
Florian Hahn
449e890f29 [SelectionDAG] Use dyn_cast without cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316258 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 05:37:10 +00:00
Florian Hahn
34f57ff3e8 [SelectionDAG] Use isa to silence unused variable warning (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316257 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 04:57:03 +00:00
Craig Topper
ba5255623c [SelectionDAG] Don't subject ConstantSDNodes to the depth limit in computeKnownBits and ComputeNumSignBits.
We don't need to do any additional recursion, we just need to analyze the APInt stored in the node. This matches what the ValueTracking versions do for IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316256 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 03:22:13 +00:00
Craig Topper
fb5a67b594 [SelectionDAG] Add a check to getVectorShuffle to ensure that the only negative index we allow is -1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316183 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-19 20:59:41 +00:00
Craig Topper
862291753b [SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to work properly for vector types.
I don't know if we ever hit this case or not. Turning it into an assert only fired on expanding some atomic operation in a SystemZ lit test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315648 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-13 00:18:58 +00:00
Craig Topper
1302400e29 [SelectionDAG} Use KnownBits::isUnknown and hasConflict. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315154 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-07 17:07:48 +00:00
Craig Topper
9bccb6a563 [SelectionDAG] Make NewSDValueDbgMsg print target specific nodes correctly by passing in the SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314271 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-27 05:17:14 +00:00
Simon Pilgrim
3632da7880 [SelectionDAG] Add BITCAST handling to ComputeNumSignBits for splatted sign bits.
For cases where we are BITCASTing to vectors of smaller elements, then if the entire source was a splatted sign (src's NumSignBits == SrcBitWidth) we can say that the dst's NumSignBit == DstBitWidth, as we're just splitting those sign bits across multiple elements.

We could generalize this but at the moment the only use case I have is to peek through bitcasts to vector comparison results.

Differential Revision: https://reviews.llvm.org/D37849

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313543 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-18 16:45:05 +00:00
Simon Pilgrim
f6a8db12f6 [SelectionDAG] ComputeNumSignBits - cleanup ROTL/ROTR wrapping to match DAGCombine etc.
Use RotAmt.urem(VTBits) instead of AND(RotAmt, VTBits - 1)

TBH I don't expect non-power-of-2 types to be created, but it makes the logic clearer and matches what we do in other rotation combines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313245 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-14 10:28:01 +00:00
Reid Kleckner
c86178ea37 Add llvm.codeview.annotation to implement MSVC __annotation
Summary:
This intrinsic represents a label with a list of associated metadata
strings. It is modelled as reading and writing inaccessible memory so
that it won't be removed as dead code. I think the intention is that the
annotation strings should appear at most once in the debug info, so I
marked it noduplicate. We are allowed to inline code with annotations as
long as we strip the annotation, but that can be done later.

Reviewers: majnemer

Subscribers: eraman, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D36904

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312569 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-05 20:14:58 +00:00
Wei Ding
75acc65cb3 Add ‘llvm.experimental.constrained.fma‘ Intrinsic.
Differential Revision: http://reviews.llvm.org/D36335

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311629 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 04:18:24 +00:00
Craig Topper
31bf47e949 [SelectionDAG] Make ISD::isConstantSplatVector always return an element sized APInt.
This partially reverts r311429 in favor of making ISD::isConstantSplatVector do something not confusing. Turns out the only other user of it was also having to deal with the weird property of it returning a smaller size.

So rather than continue to deal with this quirk everywhere, just make the interface do something sane.

Differential Revision: https://reviews.llvm.org/D37039

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311510 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-22 23:54:13 +00:00
Sjoerd Meijer
c2330d0540 [SelectionDAG] Add getNode debug messages
This adds debug messages to various functions that create new SDValue nodes.
This is e.g. useful to have during legalization, as otherwise it can prints
legalization info of nodes that did not appear in the dumps before.

Differential Revision: https://reviews.llvm.org/D36984


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311444 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-22 10:43:51 +00:00
Craig Topper
03d8600380 [X86] Prevent several calls to ISD::isConstantSplatVector from returning a narrower APInt than the original scalar type
ISD::isConstantSplatVector can shrink to the smallest splat width. But we don't check the size of the resulting APInt at all. This can cause us to misinterpret the results.

This patch just adds a flag to prevent the APInt from changing width.

Fixes PR34271.

Differential Revision: https://reviews.llvm.org/D36996

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311429 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-22 05:40:17 +00:00
Jonas Devlieghere
86286f91c5 [Debug info] Transfer DI to fragment expressions for split integer values.
This patch teaches the SDag type legalizer how to split up debug info for
integer values that are split into a hi and lo part.

(re-commit)

Differential Revision: https://reviews.llvm.org/D36805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311181 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-18 18:07:00 +00:00
Jonas Devlieghere
84dc1f35b1 Revert "[Debug info] Transfer DI to fragment expressions for split integer values."
This reverts commit r311102.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311111 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 17:58:33 +00:00
Jonas Devlieghere
6c37616078 [Debug info] Transfer DI to fragment expressions for split integer values.
This patch teaches the SDag type legalizer how to split up debug info for
integer values that are split into a hi and lo part.

Differential Revision: https://reviews.llvm.org/D36805



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311102 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 17:06:48 +00:00
Elad Cohen
dbcaf59142 [SelectionDAG] combine vextract (v1iX extract_subvector(vNiX, Idx))
into vextract(vNiX,Idx) when creating vextract with getNode().
This case appeared in AVX512 after fixing pr33349 in r310552.

Differential revision: https://reviews.llvm.org/D36571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310828 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-14 10:49:45 +00:00
Nirav Dave
1c26f410a3 [X86] Keep dependencies when constructing loads in combineStore
Summary:
Preserve chain dependecies between old and new loads constructed to
prevent loads from reordering below later stores.

Fixes PR34088.

Reviewers: craig.topper, spatel, RKSimon, efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36528

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310604 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-10 15:12:32 +00:00
Guy Blank
4a4eb4ba23 [SelectionDAG] Allow constant folding for implicitly truncating BUILD_VECTOR nodes.
In FoldConstantArithmetic, handle BUILD_VECTOR nodes that do implicit truncation on the elements.

This is similar to what is done in FoldConstantVectorArithmetic.

Differential Revision:
https://reviews.llvm.org/D36506

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310593 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-10 14:09:50 +00:00
Matt Arsenault
4bcb103953 DAG: Provide access to Pass instance from SelectionDAG
This allows accessing an analysis pass during lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309991 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-03 21:54:00 +00:00
Simon Pilgrim
e4f6153167 [SelectionDAG][X86] CombineBT - more aggressively determine demanded bits
This patch is in 2 parts:

1 - replace combineBT's use of SimplifyDemandedBits (hasOneUse only) with SelectionDAG::GetDemandedBits to more aggressively determine the lower bits used by BT.

2 - update SelectionDAG::GetDemandedBits to support ANY_EXTEND - if the demanded bits are only in the non-extended portion, then peek through and demand from the source value and then ANY_EXTEND that if we found a match.

Differential Revision: https://reviews.llvm.org/D35896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309486 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-29 14:50:25 +00:00
Adrian Prantl
0521b1a7f6 Remove the unused dbg.value offset from SelectionDAG (NFC)
Followup to r309426.
rdar://problem/33580047

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309436 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-28 21:27:35 +00:00
Simon Pilgrim
ae9f3ffd87 [DAG] Move DAGCombiner::GetDemandedBits to SelectionDAG
This patch moves the DAGCombiner::GetDemandedBits function to SelectionDAG::GetDemandedBits as a first step towards making it easier for targets to get to the source of any demanded bits without the limitations of SimplifyDemandedBits.

Differential Revision: https://reviews.llvm.org/D35841

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308983 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-25 16:36:44 +00:00
Konstantin Zhuravlyov
8f85685860 Enhance synchscope representation
OpenCL 2.0 introduces the notion of memory scopes in atomic operations to
  global and local memory. These scopes restrict how synchronization is
  achieved, which can result in improved performance.

  This change extends existing notion of synchronization scopes in LLVM to
  support arbitrary scopes expressed as target-specific strings, in addition to
  the already defined scopes (single thread, system).

  The LLVM IR and MIR syntax for expressing synchronization scopes has changed
  to use *syncscope("<scope>")*, where <scope> can be "singlethread" (this
  replaces *singlethread* keyword), or a target-specific name. As before, if
  the scope is not specified, it defaults to CrossThread/System scope.

  Implementation details:
    - Mapping from synchronization scope name/string to synchronization scope id
      is stored in LLVM context;
    - CrossThread/System and SingleThread scopes are pre-defined to efficiently
      check for known scopes without comparing strings;
    - Synchronization scope names are stored in SYNC_SCOPE_NAMES_BLOCK in
      the bitcode.

Differential Revision: https://reviews.llvm.org/D21723



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307722 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-11 22:23:00 +00:00
Nirav Dave
3f4f926b6a Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset
Relanding after rewriting undef.ll test to avoid host-dependant
endianness.

As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using
generic checks. Also, propagate missing local handling from there to
BaseIndexOffset checks.

Tests of note:

  * test/CodeGen/X86/build-vector* - Improved.
  * test/CodeGen/BPF/undef.ll - Improved store alignment allows an
    additional store merge

  * test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a
    case we already do not handle well. Here, the DAG is improved, but
    scheduling causes a code size degradation.

Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D34472

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307114 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 01:21:23 +00:00
Nirav Dave
d1814a363f Revert "[DAG] Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset"
This reverts commit r306819 which appears be exposing underlying
issues in a stage1 ppc64be build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306820 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-30 12:56:02 +00:00
Nirav Dave
8f57a78615 [DAG] Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset
As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using
generic checks. Also, propagate missing local handling from there to
BaseIndexOffset checks.

Tests of note:

  * test/CodeGen/X86/build-vector* - Improved.
  * test/CodeGen/BPF/undef.ll - Improved store alignment allows an
    additional store merge

  * test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a
    case we already do not handle well. Here, the DAG is improved, but
    scheduling causes a code size degradation.

Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D34472

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306819 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-30 12:23:41 +00:00
Hiroshi Inoue
059bd0e36c [SelectionDAG] set dereferenceable flag when expanding memcpy/memmove
When SelectionDAG expands memcpy (or memmove) call into a sequence of load and store instructions, it disregards dereferenceable flag even the source pointer is known to be dereferenceable.
This results in an assertion failure if SelectionDAG commonizes a load instruction generated for memcpy with another load instruction for the source pointer.
This patch makes SelectionDAG to set the dereferenceable flag for the load instructions properly to avoid the assertion failure.

Differential Revision: https://reviews.llvm.org/D34467




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306209 cdac9f57-aa62-4fd3-8940-286f4534e8a0
2017-06-24 15:17:38 +00:00
Sanjay Patel
98a050b9c0 [DAG] add helper to bind memop chains; NFCI
This step is just intended to reduce code duplication rather than change any functionality.

A follow-up would be to replace PPCTargetLowering::spliceIntoChain() usage with this new helper.

Differential Revision: https://reviews.llvm.org/D33649


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305192 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-12 14:41:48 +00:00
Nirav Dave
00d5002e51 Prevent RemoveDeadNodes from deleted already deleted node.
This prevents against assertion errors like PR32659 which occur from a
replacement deleting a node after it's been added to the list argument
of RemoveDeadNodes. The specific failure from PR32659 does not
currently happen, but it is still potentially possible. The underlying
cause is that the callers of the change dfunction builds up a list of
nodes to delete after having moved their uses and it possible that a
move of a later node will cause a previously deleted nodes to be
deleted.

Reviewers: bkramer, spatel, davide

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33731

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305070 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-09 12:57:35 +00:00
Simon Pilgrim
f6be5d234a [DAG] Move SelectionDAG::isCommutativeBinOp to TargetLowering.
This will allow commutation of target-specific DAG nodes in future patches

Differential Revision: https://reviews.llvm.org/D33882

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304911 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-07 14:05:04 +00:00
Chandler Carruth
e3e43d9d57 Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.

I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.

This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.

Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304787 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-06 11:49:48 +00:00
Mandeep Singh Grang
8c3abeed5e [llvm] Remove double semicolons
Reviewers: craig.topper, arsenm, mehdi_amini

Reviewed By: mehdi_amini

Subscribers: mehdi_amini, wdng, nhaehnle, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33924

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304767 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-06 05:08:36 +00:00
Eugene Zelenko
b1bd480c1c [CodeGen] Fix Windows builds which treat warnings as errors, broken in r304621.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304627 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-03 01:04:06 +00:00