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3 Commits

Author SHA1 Message Date
David Blaikie
48319238e4 Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 
This header includes CodeGen headers, and is not, itself, included by
any Target headers, so move it into CodeGen to match the layering of its
implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317647 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-11-08 01:01:31 +00:00
Eugene Zelenko
1422a67308 [AArch64] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292996 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-25 00:29:26 +00:00
Sebastian Pop
a3cf93ab26 [AArch64] Avoid generating indexed vector instructions for Exynos 
Avoid generating indexed vector instructions for Exynos. This is needed for
fmla/fmls/fmul/fmulx. For example, the instruction

  fmla v0.4s, v1.4s, v2.s[1]

is less efficient than the instructions

  dup v2.4s, v2.s[1]
  fmla v0.4s, v1.4s, v2.4s

Patch written by Abderrazek Zaafrani.

Differential Revision: https://reviews.llvm.org/D21571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283663 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-10-08 12:30:07 +00:00