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83 Commits

Author SHA1 Message Date
Matt Arsenault
b6397326b8 AMDGPU: Add max-mix-insts subtarget feature 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316553 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-25 07:00:51 +00:00
Konstantin Zhuravlyov
473d951406 AMDGPU: Do not emit deprecated notes for code object v3 
Differential Revision: https://reviews.llvm.org/D38749


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315810 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-14 15:59:07 +00:00
Matt Arsenault
d341fb0564 AMDGPU: Fix incorrect selection of pseudo-branches 
These should only be used if the machine structurizer is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315357 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-10 20:22:07 +00:00
Matt Arsenault
623647c960 AMDGPU: Remove global isGCN predicates 
These are problematic because they apply to everything,
and can easily clobber whatever more specific predicate
you are trying to add to a function.

Currently instructions use SubtargetPredicate/PredicateControl
to apply this to patterns applied to an instruction definition,
but not to free standing Pats. Add a wrapper around Pat
so the special PredicateControls requirements can be appended
to the final predicate list like how Mips does it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314742 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-03 00:06:41 +00:00
Matt Arsenault
3af6a4e447 AMDGPU: Fix typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314715 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-02 20:31:18 +00:00
Matt Arsenault
0bb6355f63 AMDGPU: Start selecting v_mad_mix_f32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312732 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-09-07 18:05:07 +00:00
Matt Arsenault
757642511d AMDGPU: Add ds_{read|write}_addtid_b32 definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312349 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-09-01 18:38:02 +00:00
Matt Arsenault
6a29a225d2 AMDGPU: Add most d16 load/store instruction definitions 
Doesn't include the tied operand necessary for the loads,
but is enough for the assembler to work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312347 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-09-01 18:36:06 +00:00
Konstantin Zhuravlyov
a698ffcfb3 AMDGPU: Fix gfx801 features 
gfx801 has 1/2 rate F64, Fast F32 FMA

Differential Revision: https://reviews.llvm.org/D36981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311694 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-24 20:03:07 +00:00
Dmitry Preobrazhensky
600899c871 [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes 
See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152

Reviewers: SamWot, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D36674

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311006 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-16 13:51:56 +00:00
Matt Arsenault
2e48864110 AMDGPU: Cleanup subtarget features 
Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
incompatible between feature strings.

Most of the test changes are due to random scheduling changes
from not having a default fullspeed model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310258 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-07 14:58:04 +00:00
Matt Arsenault
4e37712e3b AMDGPU: Fix typo in feature description 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310217 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-06 18:13:23 +00:00
Matt Arsenault
63c27053dd AMDGPU: Add instruction definitions for some scratch_* instructions 
Omit atomics for now since they probably aren't useful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308747 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-07-21 15:36:16 +00:00
Matt Arsenault
d56619e6f9 AMDGPU: Add encoding for carryless add/sub instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308639 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-07-20 17:42:47 +00:00
Sam Kolton
06ed4a14fd [AMDGPU] SDWA: several fixes for V_CVT and VOPC instructions 
Summary:
1. Instruction V_CVT_U32_F32 allow omod operand (see SIInstrInfo.td:1435). In fact this operand shouldn't be allowed here. This fix checks if SDWA pseudo instruction has OMod operand and then copy it.
2. There were several problems with support of VOPC instructions in SDWA peephole pass.

Reviewers: tstellar, arsenm, vpykhtin, airlied, kzhuravl

Subscribers: wdng, nhaehnle, yaxunl, dstuttard, tpr, sarnex, t-tye

Differential Revision: https://reviews.llvm.org/D34626

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306413 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-27 15:02:23 +00:00
Matt Arsenault
92c7507eee AMDGPU: Whitespace fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306265 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-26 03:01:36 +00:00
Sam Kolton
e88fc4046f [AMDGPU] SDWA: add support for GFX9 in peephole pass 
Summary:
Added support based on merged SDWA pseudo instructions. Now peephole allow one scalar operand, omod and clamp modifiers.
Added several subtarget features for GFX9 SDWA.
This diff also contains changes from D34026.
Depends D34026

Reviewers: vpykhtin, rampitec, arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D34241

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305986 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-22 06:26:41 +00:00
Matt Arsenault
f958f31ecf AMDGPU: Start adding global_* instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305838 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-20 19:54:14 +00:00
Wei Ding
2d0aa2e9ba AMDGPU : Fix ISA Version Definitions. 
Differential Revision: http://reviews.llvm.org/D28531

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305137 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-10 03:53:19 +00:00
Konstantin Zhuravlyov
e0fcf72467 AMDGPU: Make auto waitcnt before barrier a feature 
Differential Revision: https://reviews.llvm.org/D33793


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304571 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-02 17:40:26 +00:00
Sam Kolton
4abd85d7e5 [AMDGPU] SDWA: Add assembler support for GFX9 
Summary:
Added separate pseudo and real instruction for GFX9 SDWA instructions.
Currently supports only in assembler.
Depends D32493

Reviewers: vpykhtin, artem.tamazov

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D33132

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303620 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-05-23 10:08:55 +00:00
Matt Arsenault
0fad9cb52e AMDGPU: Add new subtarget features for gfx9 flat instructions 
Flat instructions gain an immediate offset, and 2 new
sets of segment specific flat instructions are added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302729 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-05-10 21:19:05 +00:00
Sam Kolton
74a47fb13d [AMDGPU] DPP: add support for GFX9 
Reviewers: artem.tamazov

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D32588

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301551 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-04-27 15:42:38 +00:00
Konstantin Zhuravlyov
79953642da AMDGPU/GFX9: Enable FastFMAF32 
Differential Revision: https://reviews.llvm.org/D32363


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301029 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-04-21 19:57:53 +00:00
Marek Olsak
fe4c8daa0f AMDGPU: Always use VGPR indexing on GFX9 
Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, dstuttard, tpr

Differential Revision: https://reviews.llvm.org/D31157

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298396 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-21 17:00:32 +00:00
Matt Arsenault
87fd70245a AMDGPU: Add VOP3P instruction format 
Add a few non-VOP3P but instructions related to packed.

Includes hack with dummy operands for the benefit of the assembler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296368 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-27 18:49:11 +00:00
Matt Arsenault
aac82e218f AMDGPU: Redefine clamp node as clamp 0.0-1.0 
Change implementation to use max instead of add.
min/max/med3 do not flush denormals regardless of the mode,
so it is OK to use it whether or not they are enabled.

Also allow using clamp with f16, and use knowledge
of dx10_clamp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295788 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-21 23:35:48 +00:00
Matt Arsenault
a418139e85 AMDGPU: Fix assembler subtarget predicate for gfx9 
This was accepting GFX9 instructions on VI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295557 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-18 19:12:26 +00:00
Matt Arsenault
83c857cd3a AMDGPU: Merge initial gfx9 support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295554 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-18 18:29:53 +00:00
Wei Ding
c75c94d0eb AMDGPU : Add trap handler support. 
Differential Revision: http://reviews.llvm.org/D26010

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294692 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-10 02:15:29 +00:00
Tom Stellard
f7f8a35213 Re-commit AMDGPU/GlobalISel: Add support for simple shaders 
Fix build when global-isel is disabled and fix a warning.

Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.

Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm

Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris

Differential Revision: https://reviews.llvm.org/D26730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293551 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-30 21:56:46 +00:00
Tom Stellard
78e51c03b5 Revert "AMDGPU/GlobalISel: Add support for simple shaders" 
This reverts commit r293503.

Revert while I investigate some of the buildbot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293509 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-30 17:42:41 +00:00
Tom Stellard
945c85d877 AMDGPU/GlobalISel: Add support for simple shaders 
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.

Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm

Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris

Differential Revision: https://reviews.llvm.org/D26730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293503 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-30 17:09:15 +00:00
Matt Arsenault
1aa15b49aa AMDGPU: Enable FeatureFlatForGlobal on Volcanic Islands 
Accomplishes what r292982 was supposed to, which ended up
only really making the necessary test changes.

This should be applied to the 4.0 branch.

Patch by Vedran Miletić <vedran@miletic.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293310 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-27 17:42:26 +00:00
Matt Arsenault
d019e8638a Enable FeatureFlatForGlobal on Volcanic Islands 
This switches to the workaround that HSA defaults to
for the mesa path.

This should be applied to the 4.0 branch.

Patch by Vedran Miletić <vedran@miletic.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292982 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-24 22:02:15 +00:00
Matt Arsenault
f3a691f0b0 AMDGPU: Combine fp16/fp64 subtarget features 
The same control register controls both, and are set to
the same defaults. Keep the old names around as aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292837 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-23 22:31:03 +00:00
Sam Kolton
1b647e664a [AMDGPU] Add subtarget features for SDWA/DPP 
Reviewers: vpykhtin, artem.tamazov, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D28900

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292596 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-20 10:01:25 +00:00
Marek Olsak
402e47a8a5 AMDGPU/SI: Remove XNACK feature from CI 
Summary: CI doesn't have XNACK.

Reviewers: tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289263 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-12-09 19:49:58 +00:00
Marek Olsak
29e2dd8cf4 AMDGPU/SI: Don't reserve XNACK when it's disabled 
Summary:
This frees 2 additional scalar registers.

These are results from all of my 3 patches combined:

  Polaris:
    Spilled SGPRs: 2231 -> 1517 (-32.00 %)

  Tonga:
    Spilled SGPRs: 3829 -> 2608 (-31.89 %)
    Spilled VGPRs: 100 -> 84 (-16.00 %)

  Tonga even spills SGPRs via VGPRs to scratch. That's a compute shader
  limited to 64 VGPRs.

Reviewers: tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27151

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289262 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-12-09 19:49:54 +00:00
Konstantin Zhuravlyov
9027123253 [AMDGPU] Add f16 support (VI+) 
Differential Revision: https://reviews.llvm.org/D25975


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286753 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-13 07:01:11 +00:00
Tom Stellard
0deee390af AMDGPU: Add VI i16 support 
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286464 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-10 16:02:37 +00:00
Tom Stellard
ae152bde49 Revert "AMDGPU: Add VI i16 support" 
This reverts commit r285939 and r285948.  These broke some conformance tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285995 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-04 13:06:34 +00:00
Tom Stellard
7c173dd5fa AMDGPU: Add VI i16 support 
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285939 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-03 17:13:50 +00:00
Matt Arsenault
783d67d503 AMDGPU: Whitespace fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285659 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-01 00:55:14 +00:00
Matt Arsenault
ac5efca3f0 AMDGPU: Use 1/2pi inline imm on VI 
I'm guessing at how it is supposed to be printed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285490 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-10-29 04:05:06 +00:00
Matt Arsenault
d6028cdcc7 AMDGPU: Add definitions for scalar store instructions 
Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.

This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285463 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-10-28 21:55:15 +00:00
Yaxun Liu
c93e472923 AMDGPU: Refactor processor definition to use ISA version features 
Add missing ISA versions 7.0.2/8.0.4/8.1.0. to backend.

Refactor processor definition to use ISA version features.

Fixed ISA version for stoney.

Based on Laurent Morichetti's patch.

Differential Revision: https://reviews.llvm.org/D25919

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285210 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-10-26 16:37:56 +00:00
Tom Stellard
a9c6165732 AMDGPU/SI: Don't allow unaligned scratch access 
Summary: The hardware doesn't support this.

Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D25523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284257 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-10-14 18:10:39 +00:00
Matt Arsenault
7e2ade4213 AMDGPU: Add instruction definitions for VGPR indexing 
VI added a second method of indexing into VGPRs
besides using v_movrel*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284027 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-10-12 18:00:51 +00:00
Changpeng Fang
2683a2de40 AMDGPU/SI: Update ISA version numbers for Tonga and Polaris10/11. 
Differential Revision:
  http://reviews.llvm.org/D25454

Reviewers:
  tstellarAMD

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283893 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-10-11 16:00:47 +00:00