RPCS3/archived-llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2026-01-31 01:25:19 +01:00
Code Issues Packages Projects Releases Wiki Activity
156,669 Commits 39 Branches 10 Tags
testing
Commit Graph

2 Commits

Author SHA1 Message Date
Alex Bradbury
1437cc9a52 [RISCV] Prepare for the use of variable-sized register classes 
While parameterising by XLen, also take the opportunity to clean up the 
formatting of the RISCV .td files.

This commit unifies the in-tree code with my patchset at 
<https://github.com/lowrisc/riscv-llvm>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316159 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-19 14:29:03 +00:00
Alex Bradbury
a1c2bb91ad [RISCV] Add support for disassembly 
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s
has been updated appropriately.

Differential Revision: https://reviews.llvm.org/D23567


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313486 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-09-17 14:36:28 +00:00