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testing
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5 Commits

Author SHA1 Message Date
Alex Bradbury
da781c7295 [RISCV] Initial support for function calls 
Note that this is just enough for simple function call examples to generate 
working code. Support for varargs etc follows in future patches.

Differential Revision: https://reviews.llvm.org/D29936


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317691 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-11-08 13:41:21 +00:00
Alex Bradbury
eacca308e4 [RISCV] Codegen for conditional branches 
A good portion of this patch is the extra functions that needed to be 
implemented to support the test case. e.g. storeRegToStackSlot, 
loadRegFromStackSlot, eliminateFrameIndex.

Setting ISD::BR_CC to Expand may appear non-obvious on an architecture with 
branch+cmp instructions. However, I found it much easier to deal with matching 
the expanded form.

I had to change simm13_lsb0 and simm21_lsb0 to inherit from the 
Operand<OtherVT> class rather than Operand<i32> in order to keep tablegen 
happy. This isn't a big deal, but it does seem a shame to lose the uniformity 
across immediate types when there's not an obvious benefit (I'm hoping a 
tablegen expert will educate me on what I'm missing here!).

Differential Revision: https://reviews.llvm.org/D29935


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317690 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-11-08 13:31:40 +00:00
Alex Bradbury
6c9938cf11 [RISCV] Codegen support for memory operations on global addresses 
Differential Revision: https://reviews.llvm.org/D39103


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317688 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-11-08 13:24:21 +00:00
Alex Bradbury
21ae2e7a56 [RISCV] Codegen support for memory operations 
This required the implementation of RISCVTargetInstrInfo::copyPhysReg. Support
for lowering global addresses follow in the next patch.

Differential Revision: https://reviews.llvm.org/D29934


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317685 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-11-08 12:20:01 +00:00
Alex Bradbury
5a3d179fab [RISCV] Initial codegen support for ALU operations 
This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc 
follow in future patches.

Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is 
reviewed and lands.

Differential Revision: https://reviews.llvm.org/D29933


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316188 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-19 21:37:38 +00:00