170 Commits

Author SHA1 Message Date
Sanjay Patel
da536d4e17 [InstCombine] improve demanded vector elements analysis of insertelement
Recurse instead of returning on the first found optimization. Also, return early in the caller
instead of continuing because that allows another round of simplification before we might
potentially lose undef information from a shuffle mask by eliminating the shuffle.

As noted in the review, we could probably do better and be more efficient by moving all of
demanded elements into a separate pass, but this is yet another quick fix to instcombine.

Differential Revision: https://reviews.llvm.org/D37236


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312248 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-31 15:57:17 +00:00
Craig Topper
a3ced95cbe [InstCombine] Call hasNoSignedWrap instead of hasNoUnsignedWrap to get the NSW flag when handling Add in SimplifyDemandedUseBits.
This is a typo from r311789.

This should fix PR34349.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311902 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-28 18:44:28 +00:00
Craig Topper
ef9c2d804e [InstCombine] Don't fall back to only calling computeKnownBits if the upper bit of Add/Sub is demanded.
Just create an all 1s demanded mask and continue recursing like normal. The recursive calls should be able to handle an all 1s mask and do the right thing.

The only time we should care about knowing whether the upper bit was demanded is when we need to know if we should clear the NSW/NUW flags.

Now that we have a consistent path through the code for all cases, use KnownBits::computeForAddSub to compute the known bits at the end since we already have the LHS and RHS.

My larger goal here is to move the code that turns add into xor if only 1 bit is demanded and no bits below it are non-zero from InstCombiner::OptAndOp to here. This will allow it to be more general instead of just looking for 'add' and 'and' with constant RHS.

Differential Revision: https://reviews.llvm.org/D36486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311789 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 18:39:40 +00:00
Amjad Aboud
513af851dd [InstCombine] Consider more cases where SimplifyDemandedUseBits does not convert AShr to LShr.
There are cases where AShr have better chance to be optimized than LShr, especially when the demanded bits are not known to be Zero, and also known to be similar to the sign bit.

Differential Revision: https://reviews.llvm.org/D36936




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311773 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 11:07:54 +00:00
Craig Topper
ef45a1fe1b [InstCombine] Remove unnecessary temporary APInt. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309887 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-02 21:05:40 +00:00
Craig Topper
e2cbc76f80 [InstCombine] Remove explicit check for impossible condition. Replace with assert
Summary:
As far as I can tell the earlier call getLimitedValue will guaranteed ShiftAmt is saturated to BitWidth-1 preventing it from ever being equal or greater than BitWidth.

At one point in the past the getLimitedValue call was only passed BitWidth not BitWidth - 1. This would have allowed the equality case to get here. And in fact this check was initially added as just BitWidth == ShiftAmt, but was changed shortly after to include > which should have never been possible.

Reviewers: spatel, majnemer, davide

Reviewed By: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36123

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309690 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-01 15:10:25 +00:00
Craig Topper
279ac88b99 [InstCombine] Move (0 - x) & 1 --> x & 1 to SimplifyDemandedUseBits.
This removes a dedicated matcher and allows us to support more than just an AND masking the lower bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308124 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-16 05:37:58 +00:00
Craig Topper
f552e96e02 [InstCombine] Make InstCombine's IRBuilder be passed by reference everywhere
Previously the InstCombiner class contained a pointer to an IR builder that had been passed to the constructor. Sometimes this would be passed to helper functions as either a pointer or the pointer would be dereferenced to be passed by reference.

This patch makes it a reference everywhere including the InstCombiner class itself so there is more inconsistency. This a large, but mechanical patch. I've done very minimal formatting changes on it despite what clang-format wanted to do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307451 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-07 23:16:26 +00:00
Craig Topper
6dbd34d261 [Constants] If we already have a ConstantInt*, prefer to use isZero/isOne/isMinusOne instead of isNullValue/isOneValue/isAllOnesValue inherited from Constant. NFCI
Going through the Constant methods requires redetermining that the Constant is a ConstantInt and then calling isZero/isOne/isMinusOne.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307292 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 18:39:47 +00:00
Craig Topper
eb370b4757 [InstCombine][InstSimplify] Use APInt::isNullValue/isOneValue to reduce compiled code for comparing APInts with 0 and 1. NFC
These methods are specifically optimized to only counting leading zeros without an additional uint64_t compare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-07 07:40:37 +00:00
Craig Topper
35596590b5 [InstCombine] Merge together the SimplifyDemandedUseBits implementations for ZExt and Trunc. NFC
While there avoid resizing the DemandedMask twice. Make a copy into a separate variable instead. This potentially removes an allocation on large bit widths.

With the use of the zextOrTrunc methods on APInt and KnownBits these can be made almost source identical. The only difference is the zero of the upper bits for ZExt. This is similar to how its done in computeKnownBits in ValueTracking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303791 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 18:40:25 +00:00
Craig Topper
a9efa93362 [InstCombine] Use less bitwise operations to handle Instruction::SExt in SimplifyDemandedUseBits. Other improvements.
The current code created a NewBits mask and used it as a mask several times. One of them just before a call to trunc making it unnecessary. A call to getActiveBits can get us the same information for the case. We also ORed with this mask later when we should have just sign extended the known bits.

We also called trunc on the guaranteed to be zero KnownZeros/Ones masks entering this code. Creating appropriately sized temporary APInts is probably better.

Differential Revision: https://reviews.llvm.org/D32098

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303779 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 17:33:30 +00:00
Craig Topper
5e9f2d0f5d [KnownBits] Use !hasConflict() in asserts in place of Zero & One == 0 or similar. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303614 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 07:18:37 +00:00
Craig Topper
d49344495d [KnownBits] Add bit counting methods to KnownBits struct and use them where possible
This patch adds min/max population count, leading/trailing zero/one bit counting methods.

The min methods return answers based on bits that are known without considering unknown bits. The max methods give answers taking into account the largest count that unknown bits could give.

Differential Revision: https://reviews.llvm.org/D32931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302925 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 17:20:30 +00:00
Craig Topper
ace8b39f82 [KnownBits] Add wrapper methods for setting and clear all bits in the underlying APInts in KnownBits.
This adds routines for reseting KnownBits to unknown, making the value all zeros or all ones. It also adds methods for querying if the value is zero, all ones or unknown.

Differential Revision: https://reviews.llvm.org/D32637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302262 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-05 17:36:09 +00:00
Craig Topper
f78221855b [KnownBits] Add zext, sext, and trunc methods to KnownBits
This patch adds zext, sext, and trunc methods to KnownBits and uses them where possible.

Differential Revision: https://reviews.llvm.org/D32784

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302088 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-03 22:07:25 +00:00
Craig Topper
8b69610574 [KnownBits] Add methods for determining if the known bits represent a negative/nonnegative number and add methods for changing the negative/nonnegative state
Summary: This patch adds isNegative, isNonNegative for querying whether the sign bit is known. It also adds makeNegative and makeNonNegative for controlling the sign bit.

Reviewers: RKSimon, spatel, davide

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32651

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301747 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-29 16:43:11 +00:00
Craig Topper
a7fa95c0e5 [APInt] Use inplace shift methods where possible. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301612 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-28 03:36:24 +00:00
Craig Topper
58c7fe69d0 [ValueTracking] Introduce a KnownBits struct to wrap the two APInts for computeKnownBits
This patch introduces a new KnownBits struct that wraps the two APInt used by computeKnownBits. This allows us to treat them as more of a unit.

Initially I've just altered the signatures of computeKnownBits and InstCombine's simplifyDemandedBits to pass a KnownBits reference instead of two separate APInt references. I'll do similar to the SelectionDAG version of computeKnownBits/simplifyDemandedBits as a separate patch.

I've added a constructor that allows initializing both APInts to the same bit width with a starting value of 0. This reduces the repeated pattern of initializing both APInts. Once place default constructed the APInts so I added a default constructor for those cases.

Going forward I would like to add more methods that will work on the pairs. For example trunc, zext, and sext occur on both APInts together in several places. We should probably add a clear method that can be used to clear both pieces. Maybe a method to check for conflicting information. A method to return (Zero|One) so we don't write it out everywhere. Maybe a method for (Zero|One).isAllOnesValue() to determine if all bits are known. I'm sure there are many other methods we can come up with.

Differential Revision: https://reviews.llvm.org/D32376

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301432 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-26 16:39:58 +00:00
Craig Topper
21db70eaca [APInt] Use isSubsetOf, intersects, and bit counting methods to reduce temporary APInts
This patch uses various APInt methods to reduce temporary APInt creation.

This should be all of the unrelated cleanups that got buried in D32376(creating a KnownBits struct) as well as some pointed out by Simon during the review of that. Plus a few improvements to use counting instead of masking.

I've left out any places where we do something like (KnownZero & KnownOne) != 0 as I plan to add a helper method to KnownBits to ask that question and didn't want to thrash that code an additional time.

Differential Revision: https://reviews.llvm.org/D32495

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301338 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-25 17:46:30 +00:00
Craig Topper
65c40b4fba [InstCombine] Remove superfluous curly braces around a single line if body. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301326 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-25 16:48:19 +00:00
Renato Golin
d907744fff Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API."
This reverts commit r301105, 4, 3 and 1, as a follow up of the previous
revert, which broke even more bots.

For reference:
Revert "[APInt] Use operator<<= where possible. NFC"
Revert "[APInt] Use operator<<= instead of shl where possible. NFC"
Revert "[APInt] Use ashInPlace where possible."

PR32754.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301111 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-23 12:15:30 +00:00
Craig Topper
5e17d2e85c [APInt] Use operator<<= instead of shl where possible. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301103 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-23 05:18:31 +00:00
Sanjay Patel
b51ea00f00 [InstCombine] revert r300977 and r301021
This can cause an inf-loop. Investigating...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301035 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 20:29:17 +00:00
Sanjay Patel
39af0db425 [InstCombine] use isSubsetOf() for efficiency
C | ~D == -1
~(C | ~D) == 0
~C & D == 0
D & ~C == 0
D.isSubsetOf(C)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301021 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 19:16:52 +00:00
Sanjay Patel
bd1b03d467 [InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)
This matches the demanded bits behavior in the DAG and should fix:
https://bugs.llvm.org/show_bug.cgi?id=32706

Differential Revision: https://reviews.llvm.org/D32255


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300977 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 14:03:54 +00:00
Craig Topper
c7e3512b43 [InstCombine] Remove the zextOrTrunc from ShrinkDemandedConstant.
The demanded mask and the constant should always be the same width for all callers today.

Also stop copying the demanded mask as its passed in. We should avoid allocating memory unless we are going to do something. The final AND to create the new constant will take care of it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300927 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 23:58:27 +00:00
Sanjay Patel
f23a493cab [InstCombine] function names start with lower-case letter; NFC
Forgot to make this fix with the signature change in r300911.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300912 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 22:37:01 +00:00
Sanjay Patel
e29c6aab81 [InstCombine] allow shl+shr demanded bits folds with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300911 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 22:33:54 +00:00
Sanjay Patel
a24f137360 [InstCombine] allow shl demanded bits folds with splat constants
More fixes are needed to enable the helper SimplifyShrShlDemandedBits().



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300898 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:33:02 +00:00
Craig Topper
7b99ac1139 [InstCombine] Use APInt::intersects and APInt::isSubsetOf to improve a few more places in SimplifyDemandedBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300896 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:24:37 +00:00
Sanjay Patel
f0d51838c5 [InstCombine] allow ashr/lshr demanded bits folds with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300888 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 20:59:02 +00:00
Craig Topper
a6180c4b3c [InstCombine] Use APInt::isSubsetOf to simplify some code in SimplifyDemandedBits. NFC
This allows us to use less temporary APInt for And and Invert operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300885 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 20:47:35 +00:00
Craig Topper
1fa7ca8b26 [InstCombine] Remove redundant code from SimplifyDemandedBits handling for Or. The code above it is equivalent if you work through the bitwise math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 19:31:22 +00:00
Craig Topper
54f0462d2b [APInt] Rename getSignBit to getSignMask
getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask.

Differential Revision: https://reviews.llvm.org/D32108



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300856 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 16:56:25 +00:00
Craig Topper
b52e0e4247 [APInt] Add isSubsetOf method that can check if one APInt is a subset of another without creating temporary APInts
This question comes up in many places in SimplifyDemandedBits. This makes it easy to ask without allocating additional temporary APInts.

The BitVector class provides a similar functionality through its (IMHO badly named) test(const BitVector&) method. Though its output polarity is reversed.

I've provided one example use case in this patch. I plan to do more as a follow up.

Differential Revision: https://reviews.llvm.org/D32258



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300851 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 16:17:13 +00:00
Craig Topper
1772e90779 In SimplifyDemandedUseBits, use computeKnownBits directly to handle Constants
Currently we don't explicitly process ConstantDataSequential, ConstantAggregateZero, or ConstantVector, or Undef before applying the Depth limit. Instead they occur after the depth check in the non-instruction path.

For the constant types that we do handle, the code is replicated from computeKnownBits.

This patch fixes the missing constant handling and the reduces the amount of code by just using computeKnownBits directly for any type of Constant.

Differential Revision: https://reviews.llvm.org/D32123



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300849 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 16:14:58 +00:00
Craig Topper
df22034939 [APInt] Use lshrInPlace to replace lshr where possible
This patch uses lshrInPlace to replace code where the object that lshr is called on is being overwritten with the result.

This adds an lshrInPlace(const APInt &) version as well.

Differential Revision: https://reviews.llvm.org/D32155




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-18 17:14:21 +00:00
Craig Topper
f1a890db28 Introduce APInt::isSignBitSet/isSignBitClear. Use in place isSignBitSet in place of isNegative in known bits tracking.
This makes statements like KnownZero.isNegative() (which means the value we're tracking is positive) less confusing.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300457 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-17 16:38:20 +00:00
Matt Arsenault
6d01b81485 AMDGPU: SimplifyDemandedElts for image intrinsics
Causes some VGPR usage improvements in shaderdb, but
introduces some SGPR spilling regressions due to random
scheduling changes later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300453 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-17 15:12:44 +00:00
Craig Topper
9563b95955 [InstCombine][ValueTracking] When computing known bits for Srem make sure we don't compute known bits for the LHS twice.
If we already called computeKnownBits for the RHS being a constant power of 2, we've already computed everything we can and should just stop. I think previously we would still recurse if we had determined the result was negative or had not determined the sign bit at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300432 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-16 21:46:12 +00:00
Craig Topper
bfe2c60567 [InstCombine] In SimplifyDemandedUseBits, don't bother to mask known bits of constants with DemandedMask.
Just because we didn't demand them doesn't mean they aren't known.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300430 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-16 20:55:58 +00:00
Craig Topper
61f35170e7 [InstCombine] MakeAnd/Or/Xor handling to reuse previous APInt computations
When checking if we should return a constant, we create some temporary APInts to see if we know all bits. But the exact computations we do are needed in several other locations in the same code.

This patch moves them to named temporaries so we can reuse them.

Ideally we'd write directly to KnownZero/One, but we currently seem to only write those variables after all the simplifications checks and I didn't want to change that with this patch.

Differential Revision: https://reviews.llvm.org/D32094




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300376 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 22:34:14 +00:00
Craig Topper
d62c8b3151 [InstCombine] Use APInt::setSignBit and APInt::isNegative(). NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300305 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 05:09:04 +00:00
Craig Topper
d0d13f5774 [InstCombine] Teach SimplifyMultipleUseDemandedBits to handle And/Or/Xor known bits using the LHS/RHS known bits it already acquired without recursing back into computeKnownBits.
This replicates the known bits and constant creation code from the single use case for these instructions and adds it here. The computeKnownBits and constant creation code for other instructions is now in the default case of the opcode switch.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300094 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 19:32:47 +00:00
Craig Topper
1db7e25e94 [InstCombine] Remove unreachable code for turning an And where all demanded bits on both sides are known to be zero into a constant 0.
We already handled a superset check that included the known ones too and folded to a constant that may include ones. But it can also handle the case of no ones.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300093 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 19:08:03 +00:00
Craig Topper
d9096c7391 [InstCombine] In SimplifyMultipleUseDemandedBits, use a switch instead of cascaded ifs on opcode. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300085 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:25:25 +00:00
Craig Topper
51f7e1a9dc [InstCombine] Teach SimplifyDemandedInstructionBits that even if we reach an instruction that has multiple uses, if we know all the bits for the demanded bits for this context we can go ahead and create a constant.
Currently if we reach an instruction with multiples uses we know we can't do any optimizations to that instruction itself since we only have the demanded bits for one of the users. But if we know all of the bits are zero/one for that one user we can still go ahead and create a constant to give to that user.

This might then reduce the instruction to having a single use and allow additional optimizations on the other path.

This picks up an additional case that r300075 didn't catch.

Differential Revision: https://reviews.llvm.org/D31552



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300084 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:17:46 +00:00
Craig Topper
c7bad98e0e [InstCombine] Move portion of SimplifyDemandedUseBits that deals with instructions with multiple uses out to a separate method. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300082 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:05:21 +00:00
Craig Topper
3461e9c2e4 Teach SimplifyDemandedUseBits that adding or subtractings 0s from every bit below the highest demanded bit can be simplified
If we are adding/subtractings 0s below the highest demanded bit we can just use the other operand and remove the operation.

My primary motivation is observing that we can call ShrinkDemandedConstant for the add/sub and create a 0 constant, rather than removing the add completely. In the case I saw, we modified the constant on an add instruction to a 0, but the add is not put into the worklist. So we didn't revisit it until the next InstCombine iteration. This caused an IR modification to remove add and a subsequent iteration to be ran.

With this change we get bypass the add in the first iteration and prevent the second iteration from changing anything.

Differential Revision: https://reviews.llvm.org/D31120



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300075 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 16:49:59 +00:00