Commit Graph

26717 Commits

Author SHA1 Message Date
Jonas Devlieghere
70f6aa0117 [DebugInfo] Add column info for inline sites
The column field is missing for all inline sites, currently it's always
zero. This changes populates DW_AT_call_column field for inline sites.
Test case modified to cover this change.

Patch by: Wenlei He

Differential revision: https://reviews.llvm.org/D64033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365945 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-12 19:25:45 +00:00
Fangrui Song
727b16e096 Delete dead stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365903 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-12 14:58:15 +00:00
Simon Pilgrim
a89058e1e0 [DAGCombine] narrowExtractedVectorBinOp - wrap subvector extraction in helper. NFCI.
First step towards supporting 'free' subvector extractions other than concat_vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365896 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-12 13:00:35 +00:00
Djordje Todorovic
24d43bb78f Revert "[DwarfDebug] Dump call site debug info"
A build failure was found on the SystemZ platform.

This reverts commit 9e7e73578e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365886 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-12 09:45:12 +00:00
Jinsong Ji
f85189abaa [MachinePipeliner] Fix order for nodes with Anti dependence in same cycle
Summary:
Problem exposed in PowerPC functional testing.

We did not consider Anti dependence for nodes in same cycle,
so we may end up generating bad machine code.
eg: the reduced test won't verify.

*** Bad machine code: Using an undefined physical register ***
- function:    lame_encode_buffer_interleaved
- basic block: %bb.4  (0x4bde4e12928)
- instruction: %29:gprc = ADDZE %27:gprc, implicit-def dead $carry, implicit $carry
- operand 3:   implicit $carry

Reviewers: bcahoon, kparzysz, hfinkel

Subscribers: MaskRay, wuzish, nemanjai, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64192

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365859 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-12 01:59:42 +00:00
Simon Pilgrim
554857d120 [DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
We already split extract_subvector(binop(insert_subvector(v,x),insert_subvector(w,y))) -> binop(x,y).

This patch adds support for extract_subvector(binop(concat_vectors(),concat_vectors())) cases as well.

In particular this means we don't have to wait for X86 lowering to convert concat_vectors to insert_subvector chains, which helps avoid some cases where demandedelts/combine calls occur too late to split large vector ops.

The fast-isel-store.ll load folding regression is annoying but I don't think is that critical.

Differential Revision: https://reviews.llvm.org/D63653

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365785 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-11 14:45:03 +00:00
Matt Arsenault
d160c32474 RegUsageInfoCollector: Skip calling conventions I missed before
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365784 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-11 14:41:40 +00:00
Matt Arsenault
8039567a0f GlobalISel: Use Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365780 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-11 14:18:19 +00:00
Tim Northover
f75a0e800f OpaquePtr: switch to GlobalValue::getValueType in a few places. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365770 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-11 13:13:02 +00:00
Tim Northover
2a2e351b9d OpaquePtr: use byval accessor instead of inspecting pointer type. NFC.
The accessor can deal with both "byval(ty)" and "ty* byval" forms
seamlessly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365769 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-11 13:12:38 +00:00
Sanjay Patel
4b3ebe8332 [SDAG] commute setcc operands to match a subtract
If we have:

R = sub X, Y
P = cmp Y, X

...then flipping the operands in the compare instruction can allow using a subtract that sets compare flags.

Motivated by diffs in D58875 - not sure if this changes anything there,
but this seems like a good thing independent of that.

There's a more involved version of this transform already in IR (in instcombine
although that seems misplaced to me) - see "swapMayExposeCSEOpportunities()".

Differential Revision: https://reviews.llvm.org/D63958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365711 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 23:23:54 +00:00
Amara Emerson
069ef12420 [AArch64][GlobalISel] Optimize compare and branch cases with G_INTTOPTR and unknown values.
Since we have distinct types for pointers and scalars, G_INTTOPTRs can sometimes
obstruct attempts to find constant source values. These usually come about when
try to do some kind of null pointer check. Teaching getConstantVRegValWithLookThrough
about this operation allows the CBZ/CBNZ optimization to catch more cases.

This change also improves the case where we can't find a constant source at all.
Previously we would emit a cmp, cset and tbnz for that. Now we try to just emit
a cmp and conditional branch, saving an instruction.

The cumulative code size improvement of this change plus D64354 is 5.5% geomean
on arm64 CTMark -O0.

Differential Revision: https://reviews.llvm.org/D64377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365690 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 19:21:43 +00:00
Michael Berg
4456b77e04 Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context
Summary: Unsafe does not map well alone for each of these three cases as it is missing NoNan context when accessed directly with clang.  I have migrated the fold guards to reflect the expectations of handing nan and zero contexts directly (NoNan, NSZ) and some tests with it.  Unsafe does include NSZ, however there is already precedent for using the target option directly to reflect that context. 

Reviewers: spatel, wristow, hfinkel, craig.topper, arsenm

Reviewed By: arsenm

Subscribers: michele.scandale, wdng, javed.absar

Differential Revision: https://reviews.llvm.org/D64450

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365679 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 18:23:26 +00:00
Nick Desaulniers
7cf1e3f0f2 [TargetLowering] support BlockAddress as "i" inline asm constraint
Summary:
This allows passing address of labels to inline assembly "i" input
constraints.

Fixes pr/42502.

Reviewers: ostannard

Reviewed By: ostannard

Subscribers: void, echristo, nathanchance, ostannard, javed.absar, hiraditya, llvm-commits, srhines

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365664 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 17:08:25 +00:00
Matt Arsenault
2e07d5cebb GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365658 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 16:31:19 +00:00
Matt Arsenault
a628c38932 GlobalISel: Define the full family of FP min/max instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365657 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 16:31:15 +00:00
Simon Pilgrim
14148404db [DAGCombine] visitINSERT_SUBVECTOR - use uint64_t subvector index. NFCI.
Keep the uint64_t type from getZExtValue() to stop truncation/extension overflow warnings in MSVC in subvector index math.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365621 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 12:21:35 +00:00
Simon Pilgrim
cc4f26f268 Fix const/non-const lambda return type warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365613 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 10:45:09 +00:00
Matt Arsenault
13b473d248 GlobalISel: Implement lower for G_FCOPYSIGN
In SelectionDAG AMDGPU treated these as legal, but this was mostly
because the bitcasts required for FP types were painful. Theoretically
the bitpattern should eventually match to bfi, so don't bother trying
to get the patterns to import.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365583 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 23:34:29 +00:00
Matt Arsenault
9ebcde18d1 GlobalISel: Combine unmerge of merge with intermediate cast
This eliminates some illegal intermediate vectors when operations are
scalarized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365566 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 22:19:13 +00:00
Craig Topper
d2078b8db6 [X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
Basically the problem is that X86 doesn't set the Fast flag from
allowsMemoryAccess on certain CPUs due to slow unaligned memory
subtarget features. This prevents bitcasts from being folded into
loads and stores. But all vector loads and stores of the same width
are the same cost on X86.

This patch merges the allowsMemoryAccess call into isLoadBitCastBeneficial to allow X86 to skip it.

Differential Revision: https://reviews.llvm.org/D64295

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365549 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 19:55:28 +00:00
Jinsong Ji
7e32df8cbe Revert "[HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfitable()"
This reverts commit d95557306585404893d610784edb3e32f1bfce18.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365520 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 17:53:09 +00:00
Amara Emerson
1e1e4fd87f [AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches
If we have an icmp->brcond->br sequence where the brcond just branches to the
next block jumping over the br, while the br takes the false edge, then we can
modify the conditional branch to jump to the br's target while inverting the
condition of the incoming icmp. This means we can eliminate the br as an
unconditional branch to the fallthrough block.

Differential Revision: https://reviews.llvm.org/D64354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365510 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 16:05:59 +00:00
Simon Pilgrim
8d9c5e8ad8 [DAGCombine] LoadedSlice - keep getOffsetFromBase() uint64_t offset. NFCI.
Keep the uint64_t type from getOffsetFromBase() to stop truncation/extension overflow warnings in MSVC in alignment math.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365504 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 15:28:57 +00:00
Chen Zheng
1ec7dd26c7 [HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfitable()
Differential Revision: https://reviews.llvm.org/D64197


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365497 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 14:56:17 +00:00
Petar Avramovic
47da14c083 [MIPS GlobalISel] Register bank select for G_PHI. Select i64 phi
Select gprb or fprb when def/use register operand of G_PHI is
used/defined by either:
 copy to/from physical register or
 instruction with only one mapping available for that use/def operand.

Integer s64 phi is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.

Differential Revision: https://reviews.llvm.org/D64351


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365494 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 14:36:17 +00:00
Simon Pilgrim
bd2266501a [CodeGen] AccelTable - remove non-constexpr (MSVC) Atom defs
Now that we've dropped VS2015 support (D64326) we can enable the constexpr variables on MSVC builds as VS2017+ correctly handles them


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365477 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 13:07:48 +00:00
Djordje Todorovic
f93fb8c3af [NFC][AsmPrinter] Fix the formatting for the rL365467
In addition, fix the build failure for the 'unused'
variable. The variable was used inside the 'LLVM_DEBUG()'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365469 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 12:06:21 +00:00
Tim Northover
39dc171242 OpaquePtr: add Type parameter to Loads analysis API.
This makes the functions in Loads.h require a type to be specified
independently of the pointer Value so that when pointers have no structure
other than address-space, it can still do its job.

Most callers had an obvious memory operation handy to provide this type, but a
SROA and ArgumentPromotion were doing more complicated analysis. They get
updated to merge the properties of the various instructions they were
considering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365468 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 11:35:35 +00:00
Djordje Todorovic
9e7e73578e [DwarfDebug] Dump call site debug info
Dump the DWARF information about call sites and call site parameters into
debug info sections.

The patch also provides an interface for the interpretation of instructions
that could load values of a call site parameters in order to generate DWARF
about the call site parameters.

([13/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D60716

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365467 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 11:33:56 +00:00
Bjorn Pettersson
230fbef32d [SelectionDAG] Simplify some calls to getSetCCResultType. NFC
DAGTypeLegalizer and SelectionDAGLegalize has helper
functions wrapping the call to TLI.getSetCCResultType(...).
Use those helpers in more places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365456 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 10:27:51 +00:00
Bjorn Pettersson
cb1df8b96a [LegalizeTypes] Fix saturation bug for smul.fix.sat
Summary:
Make sure we use SETGE instead of SETGT when checking
if the sign bit is zero at SMULFIXSAT expansion.

The faulty expansion occured when doing "expand" of
SMULFIXSAT and the scale was exactly matching the
size of the smaller type. For example doing
  i64 Z = SMULFIXSAT X, Y, 32
and expanding X/Y/Z into using two i32 values.

The problem was that we sometimes did not saturate
to min when overflowing.

Here is an example using Q3.4 numbers:

Consider that we are multiplying X and Y.
  X = 0x80 (-8.0 as Q3.4)
  Y = 0x20 (2.0 as Q3.4)
To avoid loss of precision we do a widening
multiplication, getting a 16 bit result
  Z = 0xF000 (-16.0 as Q7.8)

To detect negative overflow we should check if
the five most significant bits in Z are less than -1.
Assume that we name the 4 most significant bits
as HH and the next 4 bits as HL. Then we can do the
check by examining if
 (HH < -1) or (HH == -1 && "sign bit in HL is zero").

The fault was that we have been doing the check as
 (HH < -1) or (HH == -1 && HL > 0)
instead of
 (HH < -1) or (HH == -1 && HL >= 0).

In our example HH is -1 and HL is 0, so the old
code did not trigger saturation and simply truncated
the result to 0x00 (0.0). With the bugfix we instead
detect that we should saturate to min, and the result
will be set to 0x80 (-8.0).

Reviewers: leonardchan, bevinh

Reviewed By: leonardchan

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64331

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365455 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 10:24:50 +00:00
Guillaume Chatelet
64c8cde655 Fixing @llvm.memcpy not honoring volatile.
This is explicitly not addressing target-specific code, or calls to memcpy.

Summary: https://bugs.llvm.org/show_bug.cgi?id=42254

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63215

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365449 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 09:53:36 +00:00
Jeremy Morse
f0b251ebc6 Revert r364515 and r364524
Jordan reports on llvm-commits a performance regression with r364515,
backing the patch out while it's investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365448 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 09:38:03 +00:00
Djordje Todorovic
7936dfdc22 Reland "[LiveDebugValues] Emit the debug entry values"
Emit replacements for clobbered parameters location if the parameter
has unmodified value throughout the funciton. This is basic scenario
where we can use the debug entry values.

([12/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D58042

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365444 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 08:36:34 +00:00
Jinsong Ji
237a4493a0 [MachinePipeliner] Fix Phi refers to Phi in same stage in 1st epilogue
Summary:
This is exposed by functional testing on PowerPC.
In some pipelined loops, Phi refer to phi did not get value defined by
the Phi, hence getting wrong value later.

As the comment mentioned, we should "use the value defined by the Phi,
unless we're generating the firstepilog and the Phi refers to a Phi
 in a different stage.", so Phi refering to same stage Phi should use
the value defined by the Phi here.

Reviewers: bcahoon, hfinkel

Reviewed By: hfinkel

Subscribers: MaskRay, wuzish, nemanjai, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64035

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365428 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 02:27:35 +00:00
Nilanjana Basu
2a69e2802f Changing CodeView debug info type record representation in assembly files to make it more human-readable & editable & fixing bug introduced in r364987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365417 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-09 01:11:02 +00:00
Reid Kleckner
93b27c50e8 Standardize on MSVC behavior for triples with no environment
Summary:
This makes it so that IR files using triples without an environment work
out of the box, without normalizing them.

Typically, the MSVC behavior is more desirable. For example, it tends to
enable things like constant merging, use of associative comdats, etc.

Addresses PR42491

Reviewers: compnerd

Subscribers: hiraditya, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64109

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365387 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-08 21:05:20 +00:00
Matt Arsenault
f0fdc19311 RegUsageInfoCollector: Don't iterate all regs for every reg class
This is extremly slow on AMDGPU, which has a lot of physical register
and a lot of register classes.

determineCalleeSaves, via MachineRegisterInfo::isPhysRegUsed already
added all of the super registers to the saved set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365370 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-08 18:48:42 +00:00
Matt Arsenault
86ad74265e GlobalISel: Convert some build functions to using SrcOp/DstOp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365343 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-08 16:27:47 +00:00
Matt Arsenault
5213f3c6ea GlobalISel: widenScalar for G_BUILD_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365320 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-08 13:48:06 +00:00
Simon Pilgrim
a9563933b2 [TargetLowering] SimplifyDemandedBits - just call computeKnownBits for BUILD_VECTOR cases.
Don't do this locally, computeKnownBits does this better (and can handle non-constant cases as well).

A next step would be to actually simplify non-constant elements - building on what we already do in SimplifyDemandedVectorElts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365309 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-08 11:00:39 +00:00
David Majnemer
cc239d2dd8 [CodeGen] Add larger vector types for i32 and f32
Some out of tree backend require larger vector type. Since maintaining the changes out of tree is difficult due to the many manual changes needed when adding a new type we are adding it even if no backend currently use it.

Differential Revision: https://reviews.llvm.org/D64141

Patch by Thomas Raoux!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365274 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-07 04:47:37 +00:00
Simon Pilgrim
7eeed07642 [DAGCombine] convertBuildVecZextToZext - remove duplicate getOpcode() call. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365269 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-06 18:32:15 +00:00
Quentin Colombet
99e372c260 [RegisterCoalescer] Fix an overzealous assert
Although removeCopyByCommutingDef deals with full copies, it is still
possible to copy undef lanes and thus, we wouldn't have any a value
number for these lanes.

This fixes PR40215.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365256 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-06 00:34:54 +00:00
Matt Arsenault
c4a91bfbce RegUsageInfoCollector: Skip AMDGPU entry point functions
I'm not sure if it's worth it or not to add a hook to disable the pass
for an arbitrary function.

This pass is taking up to 5% of compile time in tiny programs by
iterating through all of the physical registers in every register
class. This pass should be rewritten in terms of regunits. For now,
skip doing anything for entry point functions. The vast majority of
functions in the real world aren't callable, so just not running this
will give the majority of the benefit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365255 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-05 23:33:43 +00:00
Michael Liao
0d22b740ac [CodeGen] Enhance MachineInstrSpan to allow the end of MBB to be used.
Summary:
- Explicitly specify the parent MBB to allow the end iterator to be
  used.

Reviewers: aprantl, MatzeB, craig.topper, qcolombet

Subscribers: arsenm, jvesely, nhaehnle, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64261

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365240 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-05 20:23:59 +00:00
Matt Arsenault
f5e83e90b1 ScheduleDAG: Fix incorrectly killing registers in bundles
When looking for uses/defs to add kill flags, the iterator was double
incremented, skipping the first instruction in the bundle. The use
register in the first bundle instruction was then incorrectly killed.
The "First" instruction should be the BUNDLE itself as the proper
reverse iterator endpoint.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365216 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-05 15:32:28 +00:00
Robert Lougher
a71113c59d Revert r365198 as this accidentally commited something that
should not have been added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365199 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-05 12:30:45 +00:00
Robert Lougher
a6326da30a This reverts r365061 and r365062 (test update)
Revision r365061 changed a skip of debug instructions for a skip
of meta instructions. This is not safe, as IMPLICIT_DEF is classed
as a meta instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365198 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-05 12:20:21 +00:00