Commit Graph

5 Commits

Author SHA1 Message Date
Sam Parker
3423b03f7b [ARM][LowOverheadLoops] Correct offset checking
This patch addresses a couple of problems:
1) The maximum supported offset of LE is -4094.
2) The offset of WLS also needs to be checked, this uses a
   maximum positive offset of 4094.
    
The use of BasicBlockUtils has been changed because the block offsets
weren't being initialised, but the isBBInRange checks both positive
and negative offsets.
    
ARMISelLowering has been tweaked because the test case presented
another pattern that we weren't supporting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365749 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-11 09:56:15 +00:00
Sam Parker
f45090ffa8 [NFC][ARM] Convert lambdas to static helpers
Break up and convert some of the lambdas in ARMLowOverheadLoops into
static functions. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365623 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-10 12:29:43 +00:00
Sam Parker
b74b51461d [ARM] WLS/LE Code Generation
Backend changes to enable WLS/LE low-overhead loops for armv8.1-m:
1) Use TTI to communicate to the HardwareLoop pass that we should try
   to generate intrinsics that guard the loop entry, as well as setting
   the loop trip count.
2) Lower the BRCOND that uses said intrinsic to an Arm specific node:
   ARMWLS.
3) ISelDAGToDAG the node to a new pseudo instruction:
   t2WhileLoopStart.
4) Add support in ArmLowOverheadLoops to handle the new pseudo
   instruction.

Differential Revision: https://reviews.llvm.org/D63816


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364733 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-01 08:21:28 +00:00
Sam Parker
b0917b06be [ARM] Fix for DLS/LE CodeGen
The expensive buildbots highlighted the mir tests were broken, which
I've now updated and added --verify-machineinstrs to them. This also
uncovered a couple of bugs in the backend pass, so these have also
been fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364323 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 15:11:17 +00:00
Sam Parker
580eedab52 [ARM] DLS/LE low-overhead loop code generation
Introduce three pseudo instructions to be used during DAG ISel to
represent v8.1-m low-overhead loops. One maps to set_loop_iterations
while loop_decrement_reg is lowered to two, so that we can separate
the decrement and branching operations. The pseudo instructions are
expanded pre-emission, where we can still decide whether we actually
want to generate a low-overhead loop, in a new pass:
ARMLowOverheadLoops. The pass currently bails, reverting to an sub,
icmp and br, in the cases where a call or stack spill/restore happens
between the decrement and branching instructions, or if the loop is
too large.

Differential Revision: https://reviews.llvm.org/D63476


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364288 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 10:45:51 +00:00