Commit Graph

23083 Commits

Author SHA1 Message Date
Peter Collingbourne
0bc3b75ed9 Change CallLoweringInfo::CS to be an ImmutableCallSite instead of a pointer. NFCI.
This was a use-after-free waiting to happen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309159 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-26 19:15:29 +00:00
Andrew V. Tischenko
69469a788b This patch returns proper value to indicate the case when instruction throughput can't be calculated.
Differential revision https://reviews.llvm.org/D35831


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309156 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-26 18:55:14 +00:00
Adrian Prantl
dd67a2c9ab Do a better job at emitting prefrabricated skeleton CUs.
This is a better fix than r308708 for the problem introduced in
r304020. It restores the skeleton CU testcases modified by that commit
to their original form and most importantly ensures that
frontend-generated skeleton CUs (such as used to point to Clang
modules) come after the regular CUs. This broke for DICompileUnit
nodes that don't have any immediate children because they are now
constructed lazily instead of the order in which they are listed in
!llvm.dbg.cu. After this commit we still don't guarantee that order,
but we do guarantee that empty skeletons come last.

Shipping versions of LLDB are very sensitive to the ordering of
CUs. I'll track a fix for LLDB to be more permissive separately.
This fixes a test failure in the LLDB testsuite.

rdar://problem/33357252

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309154 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-26 18:48:32 +00:00
Zvi Rackover
8ec224a8e2 DAGCombiner: Extend reduceBuildVecToTrunc to handle non-zero offset
Summary:
Adding support for combining power2-strided build_vector's where the
first build_vectori's operand is extracted from a non-zero index.

Example:

 v4i32 build_vector((extract_elt V, 1),
                    (extract_elt V, 3),
                    (extract_elt V, 5),
                    (extract_elt V, 7))
 -->
 v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)

Reviewers: delena, RKSimon, guyblank

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35700

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309108 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-26 12:57:03 +00:00
Adrian Prantl
e22b98a6ed Debug Info: Support fragmented variables in the MMI side table
This reapplies commit r309034 with a bugfix+test for inlined variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309057 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-25 23:32:59 +00:00
Adrian Prantl
7cfa553c07 Revert "Debug Info: Support fragmented variables in the MMI side table"
This reverts commit r309034 because of a sanitizer issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309035 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-25 21:50:45 +00:00
Adrian Prantl
2522046447 Debug Info: Support fragmented variables in the MMI side table
<rdar://problem/17816343>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309034 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-25 21:29:22 +00:00
Simon Pilgrim
ae9f3ffd87 [DAG] Move DAGCombiner::GetDemandedBits to SelectionDAG
This patch moves the DAGCombiner::GetDemandedBits function to SelectionDAG::GetDemandedBits as a first step towards making it easier for targets to get to the source of any demanded bits without the limitations of SimplifyDemandedBits.

Differential Revision: https://reviews.llvm.org/D35841

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308983 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-25 16:36:44 +00:00
Francois Pichet
12b7f90cfc Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELT
Summary:
Do not assume little endian architecture in DAGCombiner::visitTRUNCATE and DAGCombiner::visitEXTRACT_VECTOR_ELT.
PR33682

Reviewers: hfinkel, sdardis, RKSimon

Reviewed By: sdardis, RKSimon

Subscribers: uabelho, RKSimon, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D34990

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308960 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-25 09:40:35 +00:00
Matt Arsenault
0771376957 RA: Replace asserts related to empty live intervals
These don't exactly assert the same thing anymore, and
allow empty live intervals with non-empty uses.

Removed in r308808 and r308813.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308906 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-24 18:07:55 +00:00
Benjamin Kramer
b69a2b5cec [CodeGenPrepare] Cut off FindAllMemoryUses if there are too many uses.
This avoids excessive compile time. The case I'm looking at is
Function.cpp from an old version of LLVM that still had the giant memcmp
string matcher in it. Before r308322 this compiled in about 2 minutes,
after it, clang takes infinite* time to compile it. With this patch
we're at 5 min, which is still bad but this is a pathological case.

The cut off at 20 uses was chosen by looking at other cut-offs in LLVM
for user scanning. It's probably too high, but does the job and is very
unlikely to regress anything.

Fixes PR33900.

* I'm impatient and aborted after 15 minutes, on the bug report it was
  killed after 2h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308891 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-24 16:18:09 +00:00
Reid Kleckner
78116356ca [codeview] Emit 'D' as the cv source language for D code
This matches DMD:
522263965c/src/ddmd/backend/cv8.c (L199)

Fixes PR33899.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308890 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-24 16:16:42 +00:00
Reid Kleckner
7749c87e33 Format some case labels and shrink an anonymous namespace NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308889 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-24 16:16:17 +00:00
Petr Hosek
b12c7b1974 [CodeGen][X86] Fuchsia supports sincos* libcalls and sin+cos->sincos optimization
Patch by Roland McGrath

Differential Revision: https://reviews.llvm.org/D35748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308854 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-23 22:30:00 +00:00
Nirav Dave
484f483ab4 [DAG] Fix typo preventing some stores merges to truncated stores.
Check the actual memory type stored and not the extended value size
when considering if truncated store merge is worthwhile.

Reviewers: efriedma, RKSimon, spatel, jyknight

Reviewed By: efriedma

Subscribers: llvm-commits, nhaehnle

Differential Revision: https://reviews.llvm.org/D35623

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308833 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-23 02:06:28 +00:00
Matt Arsenault
f3c728a9f1 RA: Remove another assert on empty intervals
This case is similar to the one fixed in r308808,
except when rematerializing.

Fixes bug 33884.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308813 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-22 00:24:01 +00:00
Matt Arsenault
e59b7e46c1 RA: Remove assert on empty live intervals
This is possible if there is an undef use when
splitting the vreg during spilling.

Fixes bug 33620.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308808 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-21 23:56:13 +00:00
Xin Tong
9a714ae0d0 [DAGCombiner] Update comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308772 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-21 19:10:19 +00:00
Jonas Paulsson
ed69aeeaad [SystemZ, LoopStrengthReduce]
This patch makes LSR generate better code for SystemZ in the cases of memory
intrinsics, Load->Store pairs or comparison of immediate with memory.

In order to achieve this, the following common code changes were made:

 * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if
 LSR should do instruction-based addressing evaluations by calling
 isLegalAddressingMode() with the Instruction pointers.
 * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy
 as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address,
 not just loads or stores.

SystemZ changes:

 * isLSRCostLess() implemented with Insns first, and without ImmCost.
 * New function supportedAddressingMode() that is a helper for TTI methods
 looking at Instructions passed via pointers.

Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D35262
https://reviews.llvm.org/D35049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308729 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-21 11:59:37 +00:00
Philipp Schaad
4d98985c94 Commit access test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308712 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-21 03:51:01 +00:00
Adrian Prantl
c0093a7e21 Debug Info: Don't strip clang module skeleton CUs.
This corrects a (hopefully :-) accidental side-effect of r304020.

rdar://problem/33442618

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308708 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-21 01:24:05 +00:00
Tim Northover
a1c5e69551 GlobalISel: stop localizer putting constants before EH_LABELs
If the localizer pass puts one of its constants before the label that tells the
unwinder "jump here to handle your exception" then control-flow will skip it,
leaving uninitialized registers at runtime. That's bad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308687 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 22:58:26 +00:00
Matt Arsenault
20f8334c2a Add an ID field to StackObjects
On AMDGPU SGPR spills are really spilled to another register.
The spiller creates the spills to new frame index objects,
which is used as a placeholder.

This will eventually be replaced with a reference to a position
in a VGPR to write to and the frame index deleted. It is
most likely not a real stack location that can be shared
with another stack object.

This is a problem when StackSlotColoring decides it should
combine a frame index used for a normal VGPR spill with
a real stack location and a frame index used for an SGPR.

Add an ID field so that StackSlotColoring has a way
of knowing the different frame index types are
incompatible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308673 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 21:03:45 +00:00
Francis Visoiu Mistrih
409daa0709 [PEI] Fix refactoring from r308664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308666 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 20:31:44 +00:00
Mandeep Singh Grang
8c714df517 [COFF, ARM64, CodeView] Add support to emit CodeView debug info for ARM64 COFF
Reviewers: compnerd, ruiu, rnk, zturner

Reviewed By: rnk

Subscribers: majnemer, aemerson, aprantl, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 20:20:00 +00:00
Francis Visoiu Mistrih
c39bccc79f [PEI] Separate saving and restoring CSRs into different functions. NFC
Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308664 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 20:17:17 +00:00
Krzysztof Parzyszek
cf138ec142 Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLane
This should eliminate most uses of countPopulation and Log2_32 on
the lane mask values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308658 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 19:43:19 +00:00
Krzysztof Parzyszek
80b6fdc3a6 Use LaneBitmask::getLane in a few more places
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308655 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 19:15:56 +00:00
Nirav Dave
5de91efd2a [DAG] Commit missed nit cleanup from r308617. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308645 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 18:07:57 +00:00
Nirav Dave
7a367b65ba [DAG] Handle missing transform in fold of value extension case.
Summary:
When pushing an extension of a constant bitwise operator on a load
into the load, change other uses of the load value if they exist to
prevent the old load from persisting.

Reviewers: spatel, RKSimon, efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35030

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308618 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 13:57:32 +00:00
Nirav Dave
e7505b3af6 [DAG] Optimize away degenerate INSERT_VECTOR_ELT nodes.
Summary:
Add missing vector write of vector read reduction, i.e.:

(insert_vector_elt x (extract_vector_elt x idx) idx) to x

Reviewers: spatel, RKSimon, efriedma

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35563

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308617 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 13:48:17 +00:00
Simon Pilgrim
0f6dee58a6 [DAGCombiner] Match ISD::SRL non-uniform constant vectors patterns using predicates.
Use predicate matchers introduced in D35492 to match more ISD::SRL constant folds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308602 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 11:03:30 +00:00
Simon Pilgrim
0c953014bc Remove trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308601 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 10:43:52 +00:00
Simon Pilgrim
272cd527cc [DAGCombiner] Match ISD::SRA non-uniform constant vectors patterns using predicates.
Use predicate matchers introduced in D35492 to match more ISD::SRA constant folds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308600 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 10:43:05 +00:00
Simon Pilgrim
b16c6ff827 [DAGCombiner] Match non-uniform constant vectors using predicates.
Most combines currently recognise scalar and splat-vector constants, but not non-uniform vector constants.

This patch introduces a matching mechanism that uses predicates to check against BUILD_VECTOR of ConstantSDNode, as well as scalar ConstantSDNode cases.

I've changed a couple of predicates to demonstrate - the combine-shl changes add currently unsupported cases, while the MatchRotate replaces an existing mechanism.

Differential Revision: https://reviews.llvm.org/D35492

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308598 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 10:13:40 +00:00
Francis Visoiu Mistrih
6100762761 Revert "[PEI] Simplify handling of targets with no phys regs. NFC"
This reverts commit ce30ab6e55.

sanitizer-ppc64le-linux seems to segfault when testing the sanitizers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308581 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 02:47:05 +00:00
Francis Visoiu Mistrih
b08ebc92be Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"
This reverts commit 540f6a26ae.

sanitizer-ppc64le-linux seems to segfault when testing the sanitizers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308580 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 02:47:04 +00:00
Francis Visoiu Mistrih
540f6a26ae [PEI] Separate saving and restoring CSRs into different functions. NFC
Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308573 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 00:58:37 +00:00
Matt Arsenault
8a3fcdae02 Replace -print-whole-regmask with a threshold.
The previous flag/default of printing everything is
not helpful when there are thousands of registers
in the mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308572 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 00:37:31 +00:00
Francis Visoiu Mistrih
2bc0cace0b Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"
This reverts commit a84d1fa684.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308562 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20 00:08:02 +00:00
Francis Visoiu Mistrih
0775d243ea [AsmPrinter] Constify needsCFIMoves. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308557 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 23:47:33 +00:00
Francis Visoiu Mistrih
5418b3d4c9 [PEI] Add basic opt-remarks support
Add optimization remarks support to the PrologueEpilogueInserter. For
now, emit the stack size as an analysis remark, but more additions wrt
shrink-wrapping may be added.

https://reviews.llvm.org/D35645

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308556 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 23:47:32 +00:00
Francis Visoiu Mistrih
ce30ab6e55 [PEI] Simplify handling of targets with no phys regs. NFC
Make doSpillCalleeSavedRegs a member function, instead of passing most
of the members of PEI as arguments.

Differential Revision: https://reviews.llvm.org/D35642

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308555 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 23:47:32 +00:00
Francis Visoiu Mistrih
a84d1fa684 [PEI] Separate saving and restoring CSRs into different functions. NFC
Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308554 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 23:47:31 +00:00
Derek Schuff
acdb8f988e Move Runtime libcall definitions to a .def file
This will allow eliminating the duplication of the names, and allow adding
extra information such as signatures in a future commit.

Differential Revision: https://reviews.llvm.org/D35522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308531 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 21:53:30 +00:00
Wolfgang Pieb
a6df1e57e8 Fixing an issue with the initialization of LexicalScopes objects when mixing debug
and non-debug units.

Patch by Andrea DiBiagio.

Differential Revision:  https://reviews.llvm.org/D35637


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308513 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 19:36:40 +00:00
Simon Pilgrim
dda2d9fd06 {DAGCombine] Convert (Val & Mask) == Mask to Mask.isSubsetof(Val). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308460 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 13:39:58 +00:00
Serguei Katkov
8d9168d095 [CGP] Allow cycles during Phi traversal in OptimizaMemoryInst
Allowing cycles in Phi traversal increases the scope of optimize memory instruction
in case we are in loop.

The added test shows an example of enabling optimization inside a loop.

Reviewers: loladiro, spatel, efriedma
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35294


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308419 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 04:49:17 +00:00
Adrian Prantl
9563b5a5e1 Debug Info: Add a file: field to DIImportedEntity.
DIImportedEntity has a line number, but not a file field. To determine
the decl_line/decl_file we combine the line number from the
DIImportedEntity with the file from the DIImportedEntity's scope. This
does not work correctly when the parent scope is a DINamespace or a
DIModule, both of which do not have a source file.

This patch adds a file field to DIImportedEntity to unambiguously
identify the source location of the using/import declaration.  Most
testcase updates are mechanical, the interesting one is the removal of
the FIXME in test/DebugInfo/Generic/namespace.ll.

This fixes PR33822. See https://bugs.llvm.org/show_bug.cgi?id=33822
for more context.

<rdar://problem/33357889>
https://bugs.llvm.org/show_bug.cgi?id=33822

Differential Revision: https://reviews.llvm.org/D35583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308398 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-19 00:09:54 +00:00
Nirav Dave
ca6d3f8f6a [DAG] Improve Aliasing of operations to static alloca
Re-recommiting after landing DAG extension-crash fix.

Recommiting after adding check to avoid miscomputing alias information
on addresses of the same base but different subindices.

Memory accesses offset from frame indices may alias, e.g., we
may merge write from function arguments passed on the stack when they
are contiguous. As a result, when checking aliasing, we consider the
underlying frame index's offset from the stack pointer.

Static allocs are realized as stack objects in SelectionDAG, but its
offset is not set until post-DAG causing DAGCombiner's alias check to
consider access to static allocas to frequently alias. Modify isAlias
to consider access between static allocas and access from other frame
objects to be considered aliasing.

Many test changes are included here. Most are fixes for tests which
indirectly relied on our aliasing ability and needed to be modified to
preserve their original intent.

The remaining tests have minor improvements due to relaxed
ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll
which has a minor degradation dispite though the pre-legalized DAG is
improved.

Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand

Reviewed By: rnk

Subscribers: sdardis, nemanjai, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308350 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-18 20:06:24 +00:00