Commit Graph

5 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin
791f311a49 [AMDGPU] Use GCNRPTracker dumper methods in scheduler
Differential Revision: https://reviews.llvm.org/D33244

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303186 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-16 16:31:45 +00:00
Stanislav Mekhanoshin
e61df31e20 [AMDGPU] Turn register pressure estimation into forward tracker
This factors register pressure estimation mechanism from the
GCNSchedStrategy into the forward tracker to unify interface
with other strategies and expose it to other interested phases.

Differential Revision: https://reviews.llvm.org/D33105

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303179 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-16 15:43:52 +00:00
Stanislav Mekhanoshin
f7e315844f [AMDGPU] Fixed typo in GCNRegPressure, NFC
VGRP -> VGPR, SGRP -> SGPR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302586 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 20:50:04 +00:00
Krzysztof Parzyszek
36d7c2b2e5 Move size and alignment information of regclass to TargetRegisterInfo
1. RegisterClass::getSize() is split into two functions:
   - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const;
   - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const;
2. RegisterClass::getAlignment() is replaced by:
   - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const;

This will allow making those values depend on subtarget features in the
future.

Differential Revision: https://reviews.llvm.org/D31783


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301221 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-24 18:55:33 +00:00
Valery Pykhtin
4b7cf6c175 [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler
Differential revision: https://reviews.llvm.org/D31046

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298368 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 13:15:46 +00:00