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3 Commits

Author SHA1 Message Date
Kannan Narayanan
96d48fac54 [AMDGPU] In the new waitcnt insertion pass, use getHeader 
instead of getTopBlock to find the loop header.

Differential Revision: https://reviews.llvm.org/D32831



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302290 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-05-05 21:10:17 +00:00
Krzysztof Parzyszek
36d7c2b2e5 Move size and alignment information of regclass to TargetRegisterInfo 
1. RegisterClass::getSize() is split into two functions:
   - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const;
   - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const;
2. RegisterClass::getAlignment() is replaced by:
   - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const;

This will allow making those values depend on subtarget features in the
future.

Differential Revision: https://reviews.llvm.org/D31783


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301221 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-04-24 18:55:33 +00:00
Kannan Narayanan
d3302ddc52 [AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing. 
Based on comments in https://reviews.llvm.org/D31161.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300023 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-04-12 03:25:12 +00:00