Commit Graph

64 Commits

Author SHA1 Message Date
Matt Arsenault
a62ff5dd41 AMDGPU/GlobalISel: Legalize concat_vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350598 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-08 01:30:02 +00:00
Matt Arsenault
1720133d5c RegBankSelect: Fix copy insertion point for terminators
If a copy was needed to handle the condition of brcond, it was being
inserted before the defining instruction. Add tests for iterator edge
cases.

I find the existing code here suspect for the case where it's looking
for terminators that modify the register. It's going to insert a copy
in the middle of the terminators, which isn't allowed (it might be
necessary to have a COPY_terminator if anybody actually needs this).

Also legalize brcond for AMDGPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350595 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-08 01:22:47 +00:00
Matt Arsenault
2128ba0c85 AMDGPU/GlobalISel: RegBankSelect for carry-in
I'm not sure we should be allowing the truncate
to s1 for the inputs. It may be necessary to
create a new VCC reg bank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350592 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-08 01:09:09 +00:00
Matt Arsenault
9054ffcfc8 AMDGPU/GlobalISel: RegBankSelect for add/sub with carry out
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350589 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-08 01:03:58 +00:00
Matt Arsenault
5547f9f07e AMDGPU/GlobalISel: RegBankSelect for some fp ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349880 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-21 03:14:45 +00:00
Matt Arsenault
8043ea3725 AMDGPU/GlobalISel: Redo legality for build_vector
It seems better to avoid using the callback if possible since
there are coverage assertions which are disabled if this is used.

Also fix missing tests. Only test the legal cases since it seems
legalization for build_vector is quite lacking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349878 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-21 03:03:11 +00:00
Matt Arsenault
6493b36705 AMDGPU: Make i1/i64/v2i32 and/or/xor legal
The 64-bit types do depend on the register bank,
but that's another issue to deal with later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349716 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-20 01:35:49 +00:00
Matt Arsenault
e675164b4b AMDGPU/GlobalISel: RegBankSelect for fp conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349709 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-20 00:37:02 +00:00
Matt Arsenault
c6f008464f AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349708 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-20 00:33:49 +00:00
Matt Arsenault
5af2f5e104 AMDGPU: Legalize/regbankselect frame_index
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349468 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-18 09:46:13 +00:00
Matt Arsenault
08319618c5 AMDGPU: Legalize/regbankselect fma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349467 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-18 09:39:56 +00:00
Matt Arsenault
d38a2490f3 AMDGPU/GlobalISel: Legalize/regbankselect fneg/fabs/fsub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349463 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-18 09:19:03 +00:00
Matt Arsenault
dfc9645964 AMDGPU/GlobalISel: Legalize/regbankselect block_addr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349081 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-13 20:34:15 +00:00
Matt Arsenault
e50f44d0a3 AMDGPU/GlobalISel: Legalize f64 fadd/fmul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349014 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-13 08:27:48 +00:00
Matt Arsenault
f2ca2facab AMDGPU/GlobalISel: RegBankSelect some simple operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349012 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-13 08:23:51 +00:00
Amara Emerson
e7dca1ec05 [GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes.
This patch restricts the capability of G_MERGE_VALUES, and uses the new
G_BUILD_VECTOR and G_CONCAT_VECTORS opcodes instead in the appropriate places.

This patch also includes AArch64 support for selecting G_BUILD_VECTOR of <4 x s32>
and <2 x s64> vectors.

Differential Revisions: https://reviews.llvm.org/D53629

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348788 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-10 18:44:58 +00:00
Tom Stellard
69f718971f AMDGPU/GlobalISel: Add support for G_INTTOPTR
Summary: This is a no-op.

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D52916

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343839 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-05 04:34:09 +00:00
Matt Arsenault
7e212e4168 AMDGPU: Remove remnants of old address space mapping
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341165 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-31 05:49:54 +00:00
Tom Stellard
6779fccada AMDGPU/GlobalISel: Legalize G_INSERT
Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D49601

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337798 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-24 02:19:20 +00:00
Tom Stellard
031045ec8d AMDGPU/GlobalISel: Remove unnecessary legality constraint for G_EXTRACT
Summary:
We were marking G_EXTRACT operations unsupported if the output type
was larger than the input type.  I don't see how this could ever actually
happen, so I dropped the constraint.  Doing this makes it possible to
reuse the same legality code for G_INSERT.

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D49600

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337794 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-24 01:43:49 +00:00
Tom Stellard
1d6fd076a3 AMDGPU: Refactor Subtarget classes
Summary:
This is a follow-up to r335942.
- Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget
- Rename AMDGPUCommonSubtarget to AMDGPUSubtarget
- Merge R600Subtarget::Generation and GCNSubtarget::Generation into
  AMDGPUSubtarget::Generation.

Reviewers: arsenm, jvesely

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D49037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336851 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-11 20:59:01 +00:00
Tom Stellard
8eb696d509 AMDGPU/GlobalISel: Make IMPLICIT_DEF of all sizes < 512 legal.
Summary:
We could split sizes that are not power of two into smaller sized
G_IMPLICIT_DEF instructions, but this ends up generating
G_MERGE_VALUES instructions which we then have to handle in the instruction
selector.  Since G_IMPLICIT_DEF is really a no-op it's easier just to
keep everything that can fit into a register legal.

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D48777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336041 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-30 04:09:44 +00:00
Matt Arsenault
c4c340a047 AMDGPU/GlobalISel: Fix G_IMPLICIT_DEF for pointers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335485 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-25 15:42:12 +00:00
Tom Stellard
3e9055c7ee AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D48196

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335318 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-22 02:54:57 +00:00
Tom Stellard
20f413f83a AMDGPU/GlobalISel: legalize and select 32-bit G_SITOFP
Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D48195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335316 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-22 02:34:29 +00:00
Roman Tereshin
99f1f92235 [GlobalISel][AMDGPU] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call for AMDGPU
Reviewers: aemerson, qcolombet

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D46339

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333664 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 16:16:48 +00:00
Craig Topper
f137ed238d [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.
Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality of EVT::getEVTString(). The rest of EVT is used in codegen making CodeGen a better place for it.

The previous code converted a Type* to EVT and then called getEVTString. This was only expected to handle the primitive types from Type*. Since there only a few primitive types, we can just print them as strings directly.

Differential Revision: https://reviews.llvm.org/D45017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328806 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-29 17:21:10 +00:00
David Blaikie
b91d9a7128 Fix layering by moving ValueTypes.h from CodeGen to IR
ValueTypes.h is implemented in IR already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328397 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-23 23:58:31 +00:00
Matt Arsenault
41fae9f61a AMDGPU/GlobalISel: RegBankSelect for basic int ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327843 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-19 14:07:23 +00:00
Matt Arsenault
65181f7b75 AMDGPU/GlobalISel: Cleanup constant legality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327774 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-17 15:17:48 +00:00
Matt Arsenault
417485b734 AMDGPU/GlobalISel: Basic G_GEP legality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327773 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-17 15:17:45 +00:00
Matt Arsenault
177d1142dd AMDGPU/GlobalISel: Basic legality for load/store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327772 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-17 15:17:41 +00:00
Matt Arsenault
7f9dbc4419 AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327269 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-12 13:35:53 +00:00
Matt Arsenault
b3834e5d6b AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327267 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-12 13:35:43 +00:00
Matt Arsenault
b62dc36d6f AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo
These are the parameters x86 already uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327020 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-08 16:24:16 +00:00
Matt Arsenault
4e77263fcb AMDGPU/GlobalISel: Make some G_EXTRACTs legal
As far as I can tell legalization of weird sizes for the
output type isn't implemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326714 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-05 16:25:15 +00:00
Matt Arsenault
df1563c176 AMDGPU/GlobalISel: Mark i32->i64 zext as legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326481 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-01 20:56:21 +00:00
Matt Arsenault
78411cf894 AMDGPU/GlobalISel: Make i32 mul legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326471 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-01 19:22:05 +00:00
Matt Arsenault
435d0a8937 AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326470 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-01 19:16:52 +00:00
Matt Arsenault
5b58d668a1 AMDGPU/GlobalISel: Make i32 xor legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326466 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-01 19:09:21 +00:00
Matt Arsenault
7537e26848 AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legal
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326465 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-01 19:09:16 +00:00
Matt Arsenault
41f826cda5 AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legal
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326464 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-01 19:04:25 +00:00
Matt Arsenault
ca0bccecf5 AMDGPU/GlobalISel: Make f64 constants legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326101 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-26 17:20:43 +00:00
Yaxun Liu
2930e5c52d [AMDGPU] Change constant addr space to 4
Differential Revision: https://reviews.llvm.org/D43170


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325030 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-13 18:00:25 +00:00
Tom Stellard
d595719b5e AMDGPU/GlobalISel: Mark 32-bit G_FPTOUI as legal
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D42152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324446 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-07 04:47:59 +00:00
Daniel Sanders
41fccf273e [globalisel] Make LegalizerInfo::LegalizeAction available outside of LegalizerInfo. NFC
Summary:
The improvements to the LegalizerInfo discussed in D42244 require that
LegalizerInfo::LegalizeAction be available for use in other classes. As such,
it needs to be moved out of LegalizerInfo. This has been done separately to the
next patch to minimize the noise in that patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323669 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-29 17:37:29 +00:00
David Blaikie
e3a9b4ce3a Fix a bunch more layering of CodeGen headers that are in Target
All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, not the
other way around).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318490 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-17 01:07:10 +00:00
Tom Stellard
f94e4f3ed7 AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D38439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316815 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-27 23:57:41 +00:00
Quentin Colombet
f6eeaf64bb [GlobalISel] Make GlobalISel a non-optional library.
With this change, the GlobalISel library gets always built. In
particular, this is not possible to opt GlobalISel out of the build
using the LLVM_BUILD_GLOBAL_ISEL variable any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309990 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-03 21:52:25 +00:00
Tom Stellard
58dd3a3775 AMDGPU/GlobalISel: Mark 32-bit G_FMUL as legal
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D36218

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309898 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-02 22:56:30 +00:00