Unlike SDag, we use a separate G_GEP instruction (much simplified, only taking
a single byte offset) to preserve the pointer type information through
selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281205 91177308-0d34-0410-b5e6-96231b3b80d8
These instructions were only necessary when type information was stored in the
MachineInstr (because only generic MachineInstrs possessed a type). Now that
it's in MachineRegisterInfo, COPY and PHI work fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281037 91177308-0d34-0410-b5e6-96231b3b80d8
We want each register to have a canonical type, which means the best place to
store this is in MachineRegisterInfo rather than on every MachineInstr that
happens to use or define that register.
Most changes following from this are pretty simple (you need an MRI anyway if
you're going to be doing any transformations, so just check the type there).
But legalization doesn't really want to check redundant operands (when, for
example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's
operand type field to encode these constraints and limit legalization's work.
As an added bonus, more validation is possible, both in MachineVerifier and
MachineIRBuilder (coming soon).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281035 91177308-0d34-0410-b5e6-96231b3b80d8
They're another source of generic vregs, which are going to need a type on the
definition when we remove the register width from MachineRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280412 91177308-0d34-0410-b5e6-96231b3b80d8
There should be no functional change here, I'm just making the implementation
of "frem" (to libcall) legalization easier for a followup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279987 91177308-0d34-0410-b5e6-96231b3b80d8
No tests yet unfortunately (ConstantFolding reduces all supported constants to
ConstantInts before we get to translation). Soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279308 91177308-0d34-0410-b5e6-96231b3b80d8
This adds a G_INSERT instruction, which technically makes G_SEQUENCE redundant
(it's equivalent to a G_INSERT into an IMPLICIT_DEF). We'll leave G_SEQUENCE
for now though: it's likely to be far more common as it's a fundamental part of
legalization, so avoiding the mess and bloat of the extra IMPLICIT_DEFs is
probably worthwhile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279306 91177308-0d34-0410-b5e6-96231b3b80d8
First, make sure all types involved are represented, rather than being implicit
from the register width.
Second, canonicalize all types to scalar. These operations just act in bits and
don't care about vectors.
Also standardize spelling of Indices in the MachineIRBuilder (NFC here).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279294 91177308-0d34-0410-b5e6-96231b3b80d8
Unsigned addition and subtraction can reuse the instructions created to
legalize large width operations (i.e. both produce and consume a carry flag).
Signed operations and multiplies get a dedicated op-with-overflow instruction.
Once this is produced the two values are combined into a struct register (which
will almost always be merged with a corresponding G_EXTRACT as part of
legalization).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279278 91177308-0d34-0410-b5e6-96231b3b80d8
It's sharing the integer G_CONSTANT for now since I don't *think* it creates
any ambiguity (even on weird archs). If that turns out wrong we can create a
G_PTRCONSTANT or something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278423 91177308-0d34-0410-b5e6-96231b3b80d8
Otherwise we only materialize (shared) constants in the first function they
appear in. This doesn't go well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278351 91177308-0d34-0410-b5e6-96231b3b80d8
It's more than just inttoptr, but the others can't be tested until we have
support for non-trivial constants (they currently get unavoidably folded to a
ConstantInt).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278303 91177308-0d34-0410-b5e6-96231b3b80d8
If the value produced by the bitcast hasn't been referenced yet, we can simply
reuse the input register avoiding an unnecessary COPY instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278245 91177308-0d34-0410-b5e6-96231b3b80d8
For now put them all in the entry block. This should be correct but may give
poor runtime performance. Hopefully MachineSinking combined with
isReMaterializable can solve those issues, but if not the interface is sound
enough to support alternatives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278168 91177308-0d34-0410-b5e6-96231b3b80d8
Test is just reordering the existing functions (it would trigger for any
function after one with a phi).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277841 91177308-0d34-0410-b5e6-96231b3b80d8
These come in two variants for now: G_INTRINSIC and G_INTRINSIC_W_SIDE_EFFECTS.
We may decide to split the latter up with finer-grained restrictions later, if
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277224 91177308-0d34-0410-b5e6-96231b3b80d8
Just the basic equivalent to DAG's condbr for now, we'll get to things like
br_cc when we start doing more legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277184 91177308-0d34-0410-b5e6-96231b3b80d8
For MachineInstrBuilder, having to manually use RegState::Define is ugly and
makes register definitions clunkier than they need to be, so this adds two
convenience functions: addDef and addUse.
For MachineIRBuilder, we want to avoid BuildMI's first-reg-is-def rule because
it's hidden away and causes bugs. So this patch switches buildInstr to
returning a MachineInstrBuilder and adding *all* operands via addDef/addUse.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277176 91177308-0d34-0410-b5e6-96231b3b80d8
Pretty straightforward, the only oddity is the MachineMemOperand (which it's
surprisingly difficult to share code for).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276799 91177308-0d34-0410-b5e6-96231b3b80d8
Instead of an ad-hoc collection of "buildInstr" functions with varying numbers
of registers, this uses variadic templates to provide for as many regs as
needed!
Also make IRtranslator use new "buildBr" function instead of some weird generic
one that no-one else would really use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276762 91177308-0d34-0410-b5e6-96231b3b80d8
This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the
IRTranslator. The first two are direct translations (with 2 MachineInstr types
each). Since LLT discards information, a bitcast might become trivial and we
emit a COPY in those cases instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276690 91177308-0d34-0410-b5e6-96231b3b80d8
This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276158 91177308-0d34-0410-b5e6-96231b3b80d8
We can freeze the registers after the MachineFrameInfo has been configured (by
telling it about calls, inline asm, ...). This doesn't happen at all yet, but
will be part of IR translation.
Fixes -verify-machineinstrs assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275221 91177308-0d34-0410-b5e6-96231b3b80d8
