3 Commits

Author	SHA1	Message	Date
Sam Parker	26122d06c8	[ARM][NFC] Refactor sequential access for DSP ... With a view to support parallel operations that have their results stored to memory, refactor the consecutive access helper out so it could support stores instructions. Differential Revision: https://reviews.llvm.org/D48872 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336195 91177308-0d34-0410-b5e6-96231b3b80d8	2018-07-03 12:44:16 +00:00
Simon Pilgrim	be8c3633e0	Remove unnecessary semicolon. NFCI. ... Fixes -Wpedantic warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335901 91177308-0d34-0410-b5e6-96231b3b80d8	2018-06-28 18:37:16 +00:00
Sjoerd Meijer	ee2becd704	[ARM] Parallel DSP Pass ... Armv6 introduced instructions to perform 32-bit SIMD operations. The purpose of this pass is to do some straightforward IR pattern matching to create ACLE DSP intrinsics, which map on these 32-bit SIMD operations. Currently, only the SMLAD instruction gets recognised. This instruction performs two multiplications with 16-bit operands, and stores the result in an accumulator. We will follow this up with patches to recognise SMLAD in more cases, and also to generate other DSP instructions (like e.g. SADD16). Patch by: Sam Parker and Sjoerd Meijer Differential Revision: https://reviews.llvm.org/D48128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335850 91177308-0d34-0410-b5e6-96231b3b80d8	2018-06-28 12:55:29 +00:00