Summary:
Using c++11 enum classes ensures that only valid enum values are used
for ArchKind, ProfileKind, VersionKind and ISAKind. This removes the
need for checks that the provided values map to a proper enum value,
allows us to get rid of AK_LAST and prevents comparing values from
different enums. It also removes a bunch of static_cast
from unsigned to enum values and vice versa, at the cost of introducing
static casts to access AArch64ARCHNames and ARMARCHNames by ArchKind.
FPUKind and ArchExtKind are the only remaining old-style enum in
TargetParser.h. I think it's beneficial to keep ArchExtKind as old-style
enum, but FPUKind can be converted too, but this patch is quite big, so
could do this in a follow-up patch. I could also split this patch up a
bit, if people would prefer that.
Reviewers: rengolin, javed.absar, chandlerc, rovka
Reviewed By: rovka
Subscribers: aemerson, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D35882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309287 91177308-0d34-0410-b5e6-96231b3b80d8
Otherwise, each CPU has to manually specify the extensions it supports,
even though they have to be a superset of the base arch extensions.
And when there's redundant data there's stale data, so most of the CPUs
lie about the features they support (almost none lists AEK_FP).
Instead, do the saner thing: add the optional extensions on top of the
base extensions provided by the architecture.
The ARM TargetParser has the same behavior.
Differential Revision: https://reviews.llvm.org/D32780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302078 91177308-0d34-0410-b5e6-96231b3b80d8
That's only a required extension as of v8.1a.
Remove it from the "generic" CPU as well: it should only support the
base ISA (and binutils agrees).
Also unify the MC tests into crc.s and arm64-crc32.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302077 91177308-0d34-0410-b5e6-96231b3b80d8
r288279 mistakenly added it to all arches, but it's only available
from v8.1 onwards.
The testcase is awkward, because (I suspect) of PR32873.
Spotted by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301890 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
This is preparation for ThunderX processors that have Large
System Extension (LSE) atomic instructions, but not the
other instructions introduced by V8.1a.
This will mimic changes to GCC as described here:
https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00388.html
LSE instructions are: LD/ST<op>, CAS*, SWP
Reviewers: t.p.northover, echristo, jmolloy, rengolin
Subscribers: aemerson, mehdi_amini
Differential Revision: https://reviews.llvm.org/D26621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288279 91177308-0d34-0410-b5e6-96231b3b80d8
The ARMv8*-A descriptions in the ARM and AArch64 TargetParsers are incorrect
architecturally and mismatched to the backend descriptions.
RAS is an optional extension to ARMv8-A and ARMv8.1-A and mandatory in
ARMv8.2-A. Correct the ARMTargetParser descriptions which had this as enabled
by default in the earlier versions.
The FP16 and SPE extensions are optional in ARMv8.2-A and the backend defaults
them as off. They are not available as extensions to earlier ARMv8-A versions.
Correct the AArch64TargetParser which had these as enabled by default in all
ARMv8-A definitions.
These macros are only used to define preprocessor macros. There are no macros
yet as ACLE has not caught up with ARMv8.2-A so not possible to add a test.
Differential Revision: https://reviews.llvm.org/D23500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279078 91177308-0d34-0410-b5e6-96231b3b80d8
Add unittest to {ARM | AArch64}TargetParser,and by the way correct problems as below:
1.Correct a incorrect indexing problem in AArch64TargetParser. The architecture enumeration
is shared across ARM and AArch64 in original implementation.But In the code,I just used the
index which was offset by the ARM, and this would index into the array incorrectly. To make
AArch64 has its own arch enum,or we will do a lot of slowly iterating.
2.Correct a spelling error. The parameter of llvm::AArch64::getArchExtName.
3.Correct a writing mistake, in llvm::ARM::parseArchISA.
Differential Revision: https://reviews.llvm.org/D21785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276957 91177308-0d34-0410-b5e6-96231b3b80d8
RAS extensions are part of ARMv8.2,now supported in Clang.
Add RAS extensions support in AArch64TargetParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272533 91177308-0d34-0410-b5e6-96231b3b80d8
There's already a ARMTargetParser,now adding a similar one for aarch64.
so we can use it to do ARCH/CPU/FPU parsing in clang and llvm, instead of
string comparison.
Patch by Jojo Ma.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270687 91177308-0d34-0410-b5e6-96231b3b80d8
