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5 Commits

Author SHA1 Message Date
Alex Bradbury
a1c2bb91ad [RISCV] Add support for disassembly 
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s
has been updated appropriately.

Differential Revision: https://reviews.llvm.org/D23567


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313486 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-09-17 14:36:28 +00:00
Alex Bradbury
4f2535a46c [RISCV][NFC] Fix sorting of includes in lib/Target/RISCV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312624 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-09-06 09:21:21 +00:00
Alex Bradbury
1de4891dd5 [RISCV] Add RISCVInstPrinter and basic MC assembler tests 
With the addition of RISCVInstPrinter, it is now possible to test the basic 
operation of the RISCV MC layer.

Differential Revision: https://reviews.llvm.org/D23564


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310917 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-15 13:08:29 +00:00
Alex Bradbury
81a8ce81a8 [RISCV] Fix unused variable in RISCVMCTargetDesc. NFC 
Also, for better uniformity use TargetRegistry::RegisterMCAsmInfo rather than 
RegisterMCAsmInfoFn. Again, no functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295026 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-14 05:15:24 +00:00
Alex Bradbury
5ded6ebfad [RISCV] Add bare-bones RISC-V MCTargetDesc 
This is enough to compile and link but doesn't yet do anything particularly 
useful. Once an ASM parser and printer are added in the next two patches, the 
whole thing can be usefully tested.

Differential Revision: https://reviews.llvm.org/D23562


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285770 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-01 23:47:30 +00:00