2 Commits

Author	SHA1	Message	Date
Artem Belevich	6bc216ccf6	[NVPTX] Added support for .f16x2 instructions. ... This patch enables support for .f16x2 operations. Added new register type Float16x2. Added support for .f16x2 instructions. Added handling of vectorized loads/stores of v2f16 values. Differential Revision: https://reviews.llvm.org/D30057 Differential Revision: https://reviews.llvm.org/D30310 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296032 91177308-0d34-0410-b5e6-96231b3b80d8	2017-02-23 22:38:24 +00:00
Justin Lebar	e1e21627c0	[NVPTX] Enable the load-store vectorizer on nvptx. ... Reviewers: tra Subscribers: jholewinski, arsenm, asbirlea Differential Revision: https://reviews.llvm.org/D22592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276196 91177308-0d34-0410-b5e6-96231b3b80d8	2016-07-20 22:11:36 +00:00