Commit Graph

20147 Commits

Author SHA1 Message Date
David Majnemer
a80c0ed373 [CodeView] Truncate display names
Fundamentally, the length of a variable or function name is bound by the
maximum size of a record: 0xffff.  However, the name doesn't live in a
vacuum; other data is associated with the name, lowering the bound
further.

We would naively attempt to emit the name, causing us to assert because
the record would no-longer fit in 16-bits.  Instead, truncate the name
but preserve as much as we can.

While I have tested this locally, I've decided to not commit it due to
the test's size.

N.B.  While this behavior is undesirable, it is better than MSVC's
behavior.  They seem to truncate to ~4000 characters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263378 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-13 10:53:30 +00:00
Sanjoy Das
4f234e79a3 Make gc relocates more strongly typed; NFC
Don't use a `Value *` where we can use a stronger `GCRelocateInst *`
type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263327 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-12 02:54:27 +00:00
Simon Pilgrim
ddeaf238c9 [X86][SSE] Simplify vector LOAD + EXTEND on pre-SSE41 hardware
Improve vector extension of vectors on hardware without dedicated VSEXT/VZEXT instructions.

We already convert these to SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG but can further improve this by using the legalizer instead of prematurely splitting into legal vectors in the combine as this only properly helps for lowering to VSEXT/VZEXT.

Removes a lot of unnecessary any_extend + mask pattern - (Fix for PR25718).

Differential Revision: http://reviews.llvm.org/D17932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263303 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 22:18:05 +00:00
Quentin Colombet
36053724e3 [IRTranslator] Translate unconditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263265 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 17:28:03 +00:00
Quentin Colombet
a801132f2a [MachineIRBuilder] Rework buildInstr API to maximize code reuse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263264 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 17:27:58 +00:00
Quentin Colombet
acd8367766 [IRTranslator] Update getOrCreateVReg API to use references.
A value that we want to keep in a virtual register cannot be null.
Reflect that in the API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263263 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 17:27:54 +00:00
Quentin Colombet
743ea3e236 [MachineIRBuilder] Rename the setter of MF for consistency with the getter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263262 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 17:27:51 +00:00
Quentin Colombet
b62ecc87ce [MachineIRBuilder] Rename the setter for MBB for consistency with the getter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263261 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 17:27:47 +00:00
Quentin Colombet
3cf9237ecf [IRTranslator] Update getOrCreateBB API to use references.
A null basic block is invalid, so just pass a reference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263260 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 17:27:43 +00:00
Chad Rosier
8c362cf8d4 [misched] Fix a truncation issue from r263021.
The truncation was causing the sorting algorithm to behave oddly when comparing
positive and negative offsets.  Fortunately, this doesn't currently happen in
practice and was exposed by a WIP.  Thus, I can't test this change now, but the
follow on patch will.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263255 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 16:54:07 +00:00
Junmo Park
abc3287851 Minor code cleanups. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263200 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 07:05:32 +00:00
Junmo Park
c1b22faefa Minor code cleanup. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263196 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 05:07:07 +00:00
Pete Cooper
1ac3fbac0f Remove llvm::getDISubprogram in favor of Function::getSubprogram
llvm::getDISubprogram walks the instructions in a function, looking for one in the scope of the current function, so that it can find the !dbg entry for the subprogram itself.

Now that !dbg is attached to functions, this should not be necessary. This patch changes all uses to just query the subprogram directly on the function.

Ideally this should be NFC, but in reality its possible that a function:

has no !dbg (in which case there's likely a bug somewhere in an opt pass), or
that none of the instructions had a scope referencing the function, so we used to not find the !dbg on the function but now we will

Reviewed by Duncan Exon Smith.

Differential Revision: http://reviews.llvm.org/D18074

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263184 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 02:14:16 +00:00
Marianne Mailhot-Sarrasin
578acc5b53 Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263165 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 21:54:25 +00:00
Simon Pilgrim
86875b1fdf [X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG
Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns.

Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion).

Differential Revision: http://reviews.llvm.org/D17691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263159 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 20:40:26 +00:00
Chandler Carruth
c5266b5293 [PM] Port memdep to the new pass manager.
This is a fairly straightforward port to the new pass manager with one
exception. It removes a very questionable use of releaseMemory() in
the old pass to invalidate its caches between runs on a function.
I don't think this is really guaranteed to be safe. I've just used the
more direct port to the new PM to address this by nuking the results
object each time the pass runs. While this could cause some minor malloc
traffic increase, I don't expect the compile time performance hit to be
noticable, and it makes the correctness and other aspects of the pass
much easier to reason about. In some cases, it may make things faster by
making the sets and maps smaller with better locality. Indeed, the
measurements collected by Bruno (thanks!!!) show mostly compile time
improvements.

There is sadly very limited testing at this point as there are only two
tests of memdep, and both rely on GVN. I'll be porting GVN next and that
will exercise this heavily though.

Differential Revision: http://reviews.llvm.org/D17962

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263082 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 00:55:30 +00:00
Philip Reames
3239eb1016 [CGP] Duplicate addressing computation in cold paths if required to sink addressing mode
This patch teaches CGP to duplicate addressing mode computations into cold paths (detected via explicit cold attribute on calls) if required to let addressing mode be safely sunk into the basic block containing each load and store.

In general, duplicating code into cold blocks may result in code growth, but should not effect performance. In this case, it's better to duplicate some code than to put extra pressure on the register allocator by making it keep the address through the entirely of the fast path.

This patch only handles addressing computations, but in principal, we could implement a more general cold cold scheduling heuristic which tries to reduce register pressure in the fast path by duplicating code into the cold path. Getting the profitability of the general case right seemed likely to be challenging, so I stuck to the existing case (addressing computation) we already had.

Differential Revision: http://reviews.llvm.org/D17652



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263074 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-09 23:13:12 +00:00
Tom Stellard
026295317d SelectionDAG: Fix a crash on inline asm when output register supports multiple types
Summary:
The code in SelectionDAG did not handle the case where the
register type and output types were different, but had the same size.

Reviewers: arsenm, echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263022 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-09 16:02:52 +00:00
Chad Rosier
cd3a68c781 [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.
http://reviews.llvm.org/D17967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263021 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-09 16:00:35 +00:00
Krzysztof Parzyszek
05a0bf3589 Invoke DAG postprocessing in the post-RA scheduler
This was inadvertently omitted from r262774, which added the mutation
interface.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262939 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 16:54:20 +00:00
Hans Wennborg
56c1fb24e4 Revert r262599 "[X86][SSE] Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG"
This caused PR26870.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262935 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 16:21:41 +00:00
Krzysztof Parzyszek
965326494a Add DAG mutation interface to the DFA packetizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262930 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 15:33:51 +00:00
Justin Bogner
6fc18536b7 Re-apply "SelectionDAG: Store SDNode operands in an ArrayRecycler"
This re-applies r262886 with a fix for 32 bit platforms that have 8 byte
pointer alignment, effectively reverting r262892.

Original Message:

  Currently some SDNode operands are malloc'd, some are stored inline in
  subclasses of SDNode, and some are thrown into a BumpPtrAllocator.
  This scheme is complex, inconsistent, and makes refactoring SDNodes
  fairly difficult.

  Instead, we can allocate all of the operands using an ArrayRecycler
  that wraps a BumpPtrAllocator. This keeps the cache locality when
  iterating operands, improves locality when iterating SDNodes without
  looking at operands, and vastly simplifies the ownership semantics.

  It also means we stop overallocating SDNodes by 2-3x and will make it
  simpler to fix the rampant undefined behaviour we have in how we
  mutate SDNodes from one kind to another (See llvm.org/pr26808).

  This is NFC other than the changes in memory behaviour, and I ran some
  LNT tests to make sure this didn't hurt compile time. Not many tests
  changed: there were a couple of 1-2% regressions reported, but there
  were more improvements (of up to 4%) than regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262902 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 03:14:29 +00:00
Quentin Colombet
252dec6972 [MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR parser.
Thanks to Ahmed Bougacha for noticing!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262899 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 02:00:43 +00:00
Quentin Colombet
1f00e2d8f3 [GlobalISel] Introduce initializer method to support start/stop-after features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262896 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 01:38:55 +00:00
Quentin Colombet
13129166eb [MIR] Teach the parser/printer that generic virtual registers do not need a register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262893 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 01:17:03 +00:00
Justin Bogner
2a7cc3e509 Revert "SelectionDAG: Store SDNode operands in an ArrayRecycler"
Looks like the largest SDNode is different between 32 and 64 bit now,
so this is breaking 32 bit bots. Reverting while I figure out a fix.

This reverts r262886.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 01:07:03 +00:00
Quentin Colombet
03a69ba83b [MIR] Teach the parser how to parse complex types of generic machine instructions.
By complex types, I mean aggregate or vector types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262890 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 00:57:31 +00:00
Justin Bogner
54124b63dc SelectionDAG: Store SDNode operands in an ArrayRecycler
Currently some SDNode operands are malloc'd, some are stored inline in
subclasses of SDNode, and some are thrown into a BumpPtrAllocator.
This scheme is complex, inconsistent, and makes refactoring SDNodes
fairly difficult.

Instead, we can allocate all of the operands using an ArrayRecycler
that wraps a BumpPtrAllocator. This keeps the cache locality when
iterating operands, improves locality when iterating SDNodes without
looking at operands, and vastly simplifies the ownership semantics.

It also means we stop overallocating SDNodes by 2-3x and will make it
simpler to fix the rampant undefined behaviour we have in how we
mutate SDNodes from one kind to another (See llvm.org/pr26808).

This is NFC other than the changes in memory behaviour, and I ran some
LNT tests to make sure this didn't hurt compile time. Not many tests
changed: there were a couple of 1-2% regressions reported, but there
were more improvements (of up to 4%) than regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262886 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 00:39:51 +00:00
Quentin Colombet
4ae6fddb70 [MIR] Teach the printer how to print complex types for generic machine instructions.
Before this change, we would get the type definition in the middle
of the instruction.
E.g., %0(48) = G_ADD %struct_alias = type { i32, i16 } %edi, %edi

Now, we have just the expected type name:
%0(48) = G_ADD %struct_alias %edi, %edi


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262885 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 00:38:01 +00:00
Quentin Colombet
5809e74255 [MIR] Print the type of generic machine instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262880 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 00:29:15 +00:00
Quentin Colombet
7ed6f84652 [MIR] Teach the mir parser about types on generic machine instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262879 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-08 00:20:48 +00:00
Quentin Colombet
c101677635 [MachineInstr] Get rid of some GlobalISel ifdefs.
Now the type API is always available, but when global-isel is not
built the implementation does nothing.

Note: The implementation free of ifdefs is WIP and tracked here in PR26576.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262873 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-07 22:47:23 +00:00
Quentin Colombet
6266be0119 [MIR] Teach the MIPrinter about size for generic virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262867 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-07 21:57:52 +00:00
Quentin Colombet
d93f9aad50 [MIR] Teach the parser how to handle the size of generic virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262862 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-07 21:48:43 +00:00
Quentin Colombet
16fea2ad9c [MachineRegisterInfo] Add a method to set the size of a virtual register a posteriori.
This is required for mir testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262861 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-07 21:41:39 +00:00
Quentin Colombet
76b5b59a75 [MachineRegisterInfo] Get rid of the global-isel ifdefs.
One additional pointer is not a big deal size-wise and it makes
the code much nicer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262856 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-07 21:22:09 +00:00
Matt Arsenault
74d4df2129 DAGCombiner: Check legality before creating extract_vector_elt
Problem not hit by any in tree target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262852 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-07 21:10:09 +00:00
Craig Topper
4016ad20d2 [CodeGen] Add space-optimized EmitMergeInputChains1_2 to the DAG isel matching tables. Shaves about 5100 bytes from the X86 matcher table. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262815 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-07 07:29:12 +00:00
Krzysztof Parzyszek
0c79dd7f42 Add DAG mutation interface to the post-RA scheduler
Differential Revision: http://reviews.llvm.org/D17868


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262774 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-05 15:45:23 +00:00
Matthias Braun
35ea41f3e7 RegisterCoalescer: Remap subregister lanemasks before exchanging operands
Rematerializing and merging into a bigger register class at the same
time, requires the subregister range lanemasks getting remapped to the
new register class.

This fixes http://llvm.org/PR26805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262768 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-05 04:36:13 +00:00
Matthias Braun
817178adc7 RegisterCoalescer: Need to check DstReg+SrcReg for missing undef flags
copy coalescing with enabled subregister liveness can reveal undef uses,
previously this was only checked for the SrcReg in updateRegDefsUses()
but we need to check DstReg as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262767 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-05 04:36:10 +00:00
Matthias Braun
7f61887009 RegisterPressure: Small cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262766 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-05 04:36:08 +00:00
Michael Kuperstein
2005a3f20e [DAGCombine] Fix divrem combine not to assume div/rem type is simple.
The divrem combine assumed the type of the div/rem is simple, which isn't
necessarily true. This probably worked fine until r250825, since it only
saw legal types, but now breaks when it runs as a pre-type-legalization 
combine.

This fixes PR26835.

Differential Revision: http://reviews.llvm.org/D17878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262746 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-04 21:23:29 +00:00
Renato Golin
99ec266022 [ARM] Merging 64-bit divmod lib calls into one
When div+rem calls on the same arguments are found, the ARM back-end merges the
two calls into one __aeabi_divmod call for up to 32-bits values. However,
for 64-bit values, which also have a lib call (__aeabi_ldivmod), it wasn't
merging the calls, and thus calling ldivmod twice and spilling the temporary
results, which generated pretty bad code.

This patch legalises 64-bit lib calls for divmod, so that now all the spilling
and the second call are gone. It also relaxes the DivRem combiner a bit on the
legal type check, since it was already checking for isLegalOrCustom on every
value, so the extra check for isTypeLegal was redundant.

Second attempt, creating TLI.isOperationCustom like isOperationExpand, to make
sure we only emit valid types or the ones that were explicitly marked as custom.
Now, passing check-all and test-suite on x86, ARM and AArch64.

This patch fixes PR17193 (and a long time FIXME in the tests).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262738 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-04 19:19:36 +00:00
Teresa Johnson
474ca56a69 Change split code gen to use ThreadPool
Part of D15390.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262719 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-04 15:39:13 +00:00
Benjamin Kramer
fedf728970 Make headers self-contained again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262702 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-04 10:49:30 +00:00
Simon Pilgrim
946e6cb363 [X86][SSE] Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG
Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns.

Differential Revision: http://reviews.llvm.org/D17691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262599 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-03 09:43:28 +00:00
Renato Golin
ff17c53224 Revert "[ARM] Merging 64-bit divmod lib calls into one"
This reverts commit r262507, which broke some ARM buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262594 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-03 08:57:44 +00:00
Junmo Park
26c0c1e822 [BranchFolding] Change function name related with merging MMOs. NFC
Summary:
Removing MMOs is not our prefer behavior any more.

Reviewers: mcrosier, reames
   
Differential Revision: http://reviews.llvm.org/D17668


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262580 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-03 03:57:20 +00:00