Commit Graph

9 Commits

Author SHA1 Message Date
Teresa Johnson
9925f81075 Fix build error due to unsigned compare >= 0 in r263008 (NFC)
Fixes error from building with clang:

/usr/local/google/home/tejohnson/llvm/llvm_15/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp:407:12:
error: comparison of unsigned expression >= 0 is always true
[-Werror,-Wtautological-compare]
  if ((Imm >= 0x000) && (Imm <= 0x0ff)) {
         ~~~ ^  ~~~~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263014 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-09 14:58:23 +00:00
Sam Kolton
6e4c55e686 [AMDGPU] Assembler: Support DPP instructions.
Supprot DPP syntax as used in SP3 (except several operands syntax).
Added dpp-specific operands in td-files.
Added DPP flag to TSFlags to determine if instruction is dpp in InstPrinter.
Support for VOP2 DPP instructions in td-files.
Some tests for DPP instructions.

ToDo:
  - VOP2bInst:
    - vcc is considered as operand
    - AsmMatcher doesn't apply mnemonic aliases when parsing operands
  - v_mac_f32
  - v_nop
  - disable instructions with 64-bit operands
  - change dpp_ctrl assembler representation to conform sp3

Review: http://reviews.llvm.org/D17804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263008 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-09 12:29:31 +00:00
Nikolay Haustov
d129fa6931 [AMDGPU] Disassembler code refactored + error messages.
Idea behind this change is to make code shorter and as much common for all targets as possible. Let's even accept more code than is valid for a particular target, leaving it for the assembler to sort out.

64bit instructions decoding added.

Error\warning messages on unrecognized instructions operands added, InstPrinter allowed to print invalid operands helping to find invalid/unsupported code.

The change is massive and hard to compare with previous version, so it makes sense just to take a look on the new version. As a bonus, with a few TD changes following, it disassembles the majority of instructions. Currently it fully disassembles >300K binary source of some blas kernel.

Previous TODOs were saved whenever possible.

Patch by: Valery Pykhtin

Differential Revision: http://reviews.llvm.org/D17720

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262332 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-01 13:57:29 +00:00
Nikolay Haustov
1c038cf2fa [AMDGPU] Assembler: Basic support for MIMG
Add parsing and printing of image operands. Matches legacy sp3 assembler.
Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last.
Update SITargetLowering for new order.
Add basic MC test.
Update CodeGen tests.

Review: http://reviews.llvm.org/D17574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261995 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-26 09:51:05 +00:00
Tom Stellard
641de45f36 AMDGPU: waitcnt operand fixes
Summary:
Allow lgkmcnt up to 0xF (hardware allows that).
Fix mask for ExpCnt in AMDGPUInstPrinter.

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16314

Patch by: Nikolay Haustov

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259059 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-28 17:13:44 +00:00
Craig Topper
30e7d038e9 Remove extra forward declarations and scrub includes for all in tree InstPrinters. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256427 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-25 22:10:01 +00:00
Matt Arsenault
481eaf3a10 AMDGPU: Fix parsing of 32-bit literals with sign bit set
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251132 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-23 18:07:58 +00:00
NAKAMURA Takumi
09c0ea51ca Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248264 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:15:07 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00