Commit Graph

25310 Commits

Author SHA1 Message Date
Alexandros Lamprineas
5e1b99cf3b [SelectionDAG] swap select_cc operands to enable folding
The DAGCombiner tries to SimplifySelectCC as follows:

  select_cc(x, y, 16, 0, cc) -> shl(zext(set_cc(x, y, cc)), 4)

It can't cope with the situation of reordered operands:

  select_cc(x, y, 0, 16, cc)

In that case we just need to swap the operands and invert the Condition Code:

  select_cc(x, y, 16, 0, ~cc)

Differential Revision: https://reviews.llvm.org/D53236

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346484 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 11:09:40 +00:00
Craig Topper
46ec29de7d [SelectionDAG] Assert on the width of DemandedElts argument to computeKnownBits for all vector typed operations not just build_vector.
Fix AArch64 unit test that fails with the assertion added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346437 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-08 20:29:17 +00:00
Nirav Dave
e2baccfd07 [DAGCombine] Improve alias analysis for chain of independent stores.
FindBetterNeighborChains simulateanously improves the chain
dependencies of a chain of related stores avoiding the generation of
extra token factors. For chains longer than the GatherAllAliasDepths,
stores further down in the chain will necessarily fail, a potentially
significant waste and preventing otherwise trivial parallelization.

This patch directly parallelize the chains of stores before improving
each store. This generally improves DAG-level parallelism.

Reviewers: courbet, spatel, RKSimon, bogner, efriedma, craig.topper, rnk

Subscribers: sdardis, javed.absar, hiraditya, jrtc27, atanasyan, llvm-commits

Differential Revision: https://reviews.llvm.org/D53552

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346432 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-08 19:14:20 +00:00
David Blaikie
ab9a477d3f NFC: DebugInfo: Track the origin CU rather than just the base address for range lists
Turns out knowing more than just the base address might be useful -
specifically a future change to respect a DICompileUnit flag for the use
of base address specifiers in DWARF < 5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346380 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-08 00:35:54 +00:00
Jessica Paquette
0157cb5721 [MachineOutliner][NFC] Only map blocks which have adjacent legal instructions
If a block doesn't have any ranges of adjacent legal instructions, then it
can't have outlining candidates. There's no point in mapping legal isntructions
in situations like this.

I noticed this reduces the size of the suffix tree in sqlite3 for AArch64 at
-Oz by about 3%.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346379 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-08 00:33:38 +00:00
Jessica Paquette
de78771378 [MachineOutliner][NFC] Don't map MBBs that don't contain legal instructions
I noticed that there are lots of basic blocks that don't have enough legal
instructions in them to warrant outlining. We can skip mapping these entirely.

In sqlite3, compiled for AArch64 at -Oz, this results in a 10% reduction of
the total nodes in the suffix tree. These nodes can never be part of a
repeated substring, and so they don't impact the result at all.

Before this, there were 62128 nodes in the tree for sqlite3. After this, there
are 56457 nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346373 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-08 00:02:11 +00:00
Jessica Paquette
24b118cefd [MachineOutliner][NFC] Remove Parent field from SuffixTreeNode
This is only used for calculating ConcatLen. This isn't necessary,
since it's easily derived from the traversal setting suffix indices.

Remove that. Rename CurrIdx to CurrNodeLen to better describe what's
going on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346349 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 19:56:13 +00:00
Jessica Paquette
e8113b8c30 [MachineOutliner][NFC] Traverse suffix tree using a RepeatedSubstring iterator
This takes the traversal methods introduced in r346269 and adapts them
into an iterator. This allows the outliner to iterate over repeated substrings
within the suffix tree directly without having to initially find all of the
substrings and then iterate over them after you've found them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346345 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 19:20:55 +00:00
Jessica Paquette
fc6b6a704e [MachineOutliner] Don't store outlined function numberings on OutlinedFunction
NFC-ish. This doesn't change the behaviour of the outliner, but does make sure
that you won't end up with say

OUTLINED_FUNCTION_2:
...
ret

OUTLINED_FUNCTION_248:
...
ret

as the only outlined functions in your module. Those should really be

OUTLINED_FUNCTION_0:
...
ret

OUTLINED_FUNCTION_1:
...
ret

If we produce outlined functions, they probably should have sequential numbers
attached to them. This makes it a bit easier+stable to write outliner tests.

The point of this is to move towards a bit more stability in outlined function
names. By doing this, we at least don't rely on the traversal order of the
suffix tree. Instead, we rely on the order of the candidate list, which is
*far* more consistent. The candidate list is ordered by the end indices of
candidates, so we're more likely to get a stable ordering. This is still
susceptible to changes in the cost model though (like, if we suddenly find new
candidates, for example).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346340 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 18:36:43 +00:00
Serge Guelton
7c7c0a2cd9 Fix ignorded type qualifier warning [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346332 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 16:17:30 +00:00
James Y Knight
3125e35140 Add support for llvm.is.constant intrinsic (PR4898)
This adds the llvm-side support for post-inlining evaluation of the
__builtin_constant_p GCC intrinsic.

Also fixed SCCPSolver::visitCallSite to not blow up when seeing a call
to a function where canConstantFoldTo returns true, and one of the
arguments is a struct.

Updated from patch initially by Janusz Sobczak.

Differential Revision: https://reviews.llvm.org/D4276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346322 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 15:24:12 +00:00
Matthias Braun
b7a96d6f83 RegAllocFast: Leave unassigned virtreg entries in map
Set `LiveReg::PhysReg` to zero when freeing a register instead of
removing it from the entry from `LiveRegMap`. This way no iterators get
invalidated and we can avoid passing around and updating iterators all
over the place.

This does not change any allocator decisions. It is not completely NFC
because the arbitrary iteration order through `LiveRegMap` in
`spillAll()` changes so we may get a different order in those spill
sequences (the amount of spills does not change).

This is in preparation of https://reviews.llvm.org/D52010.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346298 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 06:57:03 +00:00
Matthias Braun
b8a4e3806c RegAllocFast: Further cleanups; NFC
This is in preparation of https://reviews.llvm.org/D52010.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346297 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 06:57:02 +00:00
Matthias Braun
2c10712291 RegAllocFast: Refactor PhysRegState usage; NFC
This is in preparation of https://reviews.llvm.org/D52010.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346296 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 06:57:00 +00:00
Matthias Braun
a2606fd7a7 RegAllocFast: Factor spill/reload creation into their own functions; NFC
This is in preparation of https://reviews.llvm.org/D52010.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346289 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 02:04:12 +00:00
Matthias Braun
a007c003b5 RegAllocFast: Cleanups; NFC
This is in preparation of https://reviews.llvm.org/D52010.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346288 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 02:04:11 +00:00
Matthias Braun
f41ebcbed2 RegAllocFast: Rename statistic from NumCopies to NumCoalesced
The metric does not return the number of remaining (or inserted) copies
but the number of copies that were coalesced. Pick a more descriptive
name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346287 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 02:04:07 +00:00
Jessica Paquette
4e5e34ac8f [MachineOutliner][NFC] Remove OccurrenceCount from SuffixTreeNode
After changing the way we find candidates in r346269, this is no longer used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346275 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-06 22:23:13 +00:00
Jessica Paquette
d2bfbec96c [MachineOutliner][NFC] Remove IsInTree from SuffixTreeNode
After changing the way we find repeated substrings in r346269, this
field is no longer used by anything, so it can be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346274 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-06 22:21:11 +00:00
Jessica Paquette
3d04968f30 [MachineOutliner][NFC] Add findRepeatedSubstrings to SuffixTree, kill LeafVector
Instead of iterating over the leaves to find repeated substrings, and walking
collecting leaf children when we don't necessarily need them, let's just
calculate what we need and iterate over that.

By doing this, we don't have to save every leaf. It's easier to read the code
too and understand what's going on.

The goal here, at the end of the day, is to set up to allow us to do something
like

for (RepeatedSubstring &RS : ST) {
 ... do stuff with RS ...
}

Which would let us perform the cost model stuff and the repeated substring
query at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346269 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-06 21:46:41 +00:00
Matthias Braun
27ad7c20cc LivePhysRegs/IfConversion: Change some types from unsigned to MCPhysReg; NFC
Change the type in a couple of lists and sets that only store physical
registers from unsigned to MCPhysRegs. The later is only 16bits and
saves us a bit of memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346254 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-06 19:00:11 +00:00
Matthias Braun
dad0df638d MachineFunction: Store more specific reference to LLVMTargetMachine; NFC
MachineFunction can only be used in code using lib/CodeGen, hence we
can keep a more specific reference to LLVMTargetMachine rather than just
TargetMachine around.

Do the same for references in ScheduleDAG and RegUsageInfoCollector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346183 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 23:49:14 +00:00
Matthias Braun
51c2c7a40e MachineModuleInfo: Store more specific reference to LLVMTargetMachine; NFC
MachineModuleInfo can only be used in code using lib/CodeGen, hence we
can keep a more specific reference to LLVMTargetMachine rather than just
TargetMachine around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346182 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 23:49:13 +00:00
Cameron McInally
7c442634fa [FPEnv] Add constrained CEIL/FLOOR/ROUND/TRUNC intrinsics
Differential Revision: https://reviews.llvm.org/D53411



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346141 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 15:59:49 +00:00
Simon Pilgrim
e3b515280e [TargetLowering] Begin generalizing TargetLowering::expandFP_TO_SINT support. NFCI.
Prior to initial work to add vector expansion support, remove assumptions that we're working on scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346139 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 15:49:09 +00:00
Craig Topper
29dd59de7e [DAGCombiner] Use tryFoldToZero to simplify some code and make it work correctly between LegalTypes and LegalOperations.
The original code avoided creating a zero vector after type legalization, but if we're after type legalization the type we have is legal. The real hazard we need to avoid is creating a build vector after op legalization. tryFoldToZero takes care of checking for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346119 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 05:53:06 +00:00
Craig Topper
8fe35cc92b [DAGCombiner] Remove an unused argument from tryFoldToZero. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346118 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 05:53:03 +00:00
Craig Topper
88f96230a8 [DAGCombiner] Remove 'else' after return. NFC
This makes this code consistent with the nearly identical code in visitZERO_EXTEND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346090 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-04 06:56:32 +00:00
Craig Topper
3ba729d270 [SelectionDAG] Remove special methods for creating *_EXTEND_VECTOR_INREG nodes. Move asserts into getNode.
These methods were just wrappers around getNode with additional asserts (identical and repeated 3 times). But getNode already has a switch that can be used to hold these asserts that allows them to be shared for all 3 opcodes. This also enables checking on the places that create these nodes without using the wrappers.

The rest of the patch is just changing all callers to use getNode directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346087 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-04 02:10:18 +00:00
Reid Kleckner
cc8a1a635b [codeview] Let the X86 backend tell us the VFRAME offset adjustment
Use MachineFrameInfo's OffsetAdjustment field to pass this information
from the target to CodeViewDebug.cpp. The X86 backend doesn't use it for
any other purpose.

This fixes PR38857 in the case where there is a non-aligned quantity of
CSRs and a non-aligned quantity of locals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346062 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-03 00:41:52 +00:00
Craig Topper
83e97cbe0d [X86] Don't emit *_extend_vector_inreg nodes when both the input and output types are legal with AVX1
We already have custom lowering for the AVX case in LegalizeVectorOps. So its better to keep the regular extend op around as long as possible.

I had to qualify one place in DAG combine that created illegal vector extending load operations. This change by itself had no effect on any tests which is why its included here.

I've made a few cleanups to the custom lowering. The sign extend code no longer creates an identity shuffle with undef elements. The zero extend code now emits a zero_extend_vector_inreg instead of an unpckl with a zero vector.

For the high half of the custom lowering of zero_extend/any_extend, we're now using an unpckh with a zero vector or undef. Previously we used used a pshufd to move the upper 64-bits to the lower 64-bits and then used a zero_extend_vector_inreg. I think the zero vector should require less execution resources and be smaller code size.

Differential Revision: https://reviews.llvm.org/D54024

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346043 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-02 21:09:49 +00:00
Jeremy Morse
2033b5aeb4 [MachineSink][DebugInfo] Correctly sink DBG_VALUEs
As reported in PR38952, postra-machine-sink relies on DBG_VALUE insns being
adjacent to the def of the register that they reference. This is not always
true, leading to register copies being sunk but not the associated DBG_VALUEs,
which gives the debugger a bad variable location.

This patch collects DBG_VALUEs as we walk through a BB looking for copies to
sink, then passes them down to performSink. Compile-time impact should be
negligable.

Differential Revision: https://reviews.llvm.org/D53992


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345996 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-02 16:52:48 +00:00
Simon Pilgrim
44ee005685 [DAGCombiner] Remove reduceBuildVecConvertToConvertBuildVec and rely on the vectorizers instead (PR35732)
reduceBuildVecConvertToConvertBuildVec vectorizes int2float in the DAGCombiner, which means that even if the LV/SLP has decided to keep scalar code using the cost models, this will override this.

While there are cases where vectorization is necessary in the DAG (mainly due to legalization artefacts), I don't think this is the case here, we should assume that the vectorizers know what they are doing.

Differential Revision: https://reviews.llvm.org/D53712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345964 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-02 11:06:18 +00:00
Matthias Braun
94f7fc2ccd LLVMTargetMachine/TargetPassConfig: Simplify handling of start/stop options; NFC
- Make some TargetPassConfig methods that just check whether options have
  been set static.
- Shuffle code in LLVMTargetMachine around so addPassesToGenerateCode
  only deals with TargetPassConfig now (but not with MCContext or the
  creation of MachineModuleInfo)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345918 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-02 01:31:50 +00:00
Mandeep Singh Grang
08238b7fa9 [COFF, ARM64] Implement Intrinsic.sponentry for AArch64
Summary: This patch adds Intrinsic.sponentry. This intrinsic is required to correctly support setjmp for AArch64 Windows platform.

Patch by: Yin Ma (yinma@codeaurora.org)

Reviewers: mgrang, ssijaric, eli.friedman, TomTan, mstorsjo, rnk, compnerd, efriedma

Reviewed By: efriedma

Subscribers: efriedma, javed.absar, kristof.beyls, chrib, llvm-commits

Differential Revision: https://reviews.llvm.org/D53996

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345909 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 23:22:25 +00:00
Craig Topper
41672bb1ce [DAGCombiner] Make the isTruncateOf call from visitZERO_EXTEND work for vectors. Remove FIXME.
I'm having trouble creating a test case for the ISD::TRUNCATE part of this that shows any codegen differences. But I was able to test the setcc path which is what the test changes here cover.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345908 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 23:21:45 +00:00
Jessica Paquette
41e2e9fdff [MachineOutliner][NFC] Remember when you map something illegal across MBBs
Instruction mapping in the outliner uses "illegal numbers" to signify that
something can't ever be part of an outlining candidate. This means that the
number is unique and can't be part of any repeated substring.

Because each of these is unique, we can use a single unique number to represent
a range of things we can't outline.

The outliner tries to leverage this using a flag which is set in an MBB when
the previous instruction we tried to map was "illegal". This patch improves
that logic to work across MBBs. As a bonus, this also simplifies the mapping
logic somewhat.

This also updates the machine-outliner-remarks test, which was impacted by the
order of Candidates on an OutlinedFunction changing. This order isn't
guaranteed, so I added a FIXME to fix that in a follow-up. The order of
Candidates on an OutlinedFunction isn't important, so this still is NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345906 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 23:09:06 +00:00
Simon Pilgrim
03e8599949 [LegalizeDAG] Add generic vector CTPOP expansion (PR32655)
This patch adds support for expanding vector CTPOP instructions and removes the x86 'bitmath' lowering which replicates the same expansion.

Differential Revision: https://reviews.llvm.org/D53258

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345869 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 18:22:11 +00:00
Mandeep Singh Grang
fb61af32fa Revert "[COFF, ARM64] Implement Intrinsic.sponentry for AArch64"
This reverts commit 585b6667b4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345863 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 17:53:57 +00:00
Sanjay Patel
69778b6a71 [DAGCombiner] make sure we have a whole-number extract before trying to narrow a vector op (PR39511)
The test causes a crash because we were trying to extract v4f32 to v3f32, and the
narrowing factor was then 4/3 = 1 producing a bogus narrow type.

This should fix:
https://bugs.llvm.org/show_bug.cgi?id=39511


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345842 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 15:41:12 +00:00
Zachary Turner
fd25d2bf30 [CodeView] Emit the correct TypeIndex for std::nullptr_t.
The TypeIndex used by cl.exe is 0x103, which indicates a SimpleTypeMode
of NearPointer (note the absence of the bitness, normally pointers use a
mode of NearPointer32 or NearPointer64) and a SimpleTypeKind of void.
So this is basically a void*, but without a specified size, which makes
sense given how std::nullptr_t is defined.

clang-cl was actually not emitting *anything* for this. Instead, when we
encountered std::nullptr_t in a DIType, we would actually just emit a
TypeIndex of 0, which is obviously wrong.

std::nullptr_t in DWARF is represented as a DW_TAG_unspecified_type with
a name of "decltype(nullptr)", so we add that logic along with a test,
as well as an update to the dumping code so that we no longer print
void* when dumping 0x103 (which would previously treat Void/NearPointer
no differently than Void/NearPointer64).

Differential Revision: https://reviews.llvm.org/D53957

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345811 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 04:02:41 +00:00
Mandeep Singh Grang
585b6667b4 [COFF, ARM64] Implement Intrinsic.sponentry for AArch64
Summary: This patch adds Intrinsic.sponentry. This intrinsic is required to correctly support setjmp for AArch64 Windows platform.

Reviewers: mgrang, TomTan, rnk, compnerd, mstorsjo, efriedma

Reviewed By: efriedma

Subscribers: majnemer, chrib, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D53673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345791 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 23:16:20 +00:00
Stanislav Mekhanoshin
832efd7ec3 Check shouldReduceLoadWidth from SimplifySetCC
SimplifySetCC could shrink a load without checking for
profitability or legality of such shink with a target.

Added checks to prevent shrinking of aligned scalar loads
in AMDGPU below dword as scalar engine does not support it.

Differential Revision: https://reviews.llvm.org/D53846

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345778 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 21:24:30 +00:00
Scott Linder
30005234d7 [SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt
lowerRangeToAssertZExt currently relies on something like EarlyCSE having
eliminated the constant range [0,1). At -O0 this leads to an assert.

Differential Revision: https://reviews.llvm.org/D53888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345770 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 19:57:36 +00:00
Craig Topper
b52849d771 [SelectionDAGISel] Suppress a -Wunused-but-set-variable warning in release builds. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345761 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 18:46:15 +00:00
Simon Pilgrim
ed6d50a5c3 Fix comment typo. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345758 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 18:19:52 +00:00
Simon Pilgrim
94e927ca2e [SelectionDAG] SelectionDAGLegalize::ExpandBITREVERSE - ensure we use ShiftTy
We should be using the getShiftAmountTy value type for shift amounts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345756 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 18:14:14 +00:00
Daniel Sanders
99c33171a1 [globalisel][irtranslator] Verify that DILocations aren't lost in translation
Summary:
Also fix a couple bugs where DILocations are lost. EntryBuilder wasn't passing
on debug locations for PHI's, constants, GLOBAL_VALUE, etc.

Reviewers: aprantl, vsk, bogner, aditya_nandakumar, volkan, rtereshin, aemerson

Reviewed By: aemerson

Subscribers: aemerson, rovka, kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D53740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345743 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 17:31:23 +00:00
Matthias Braun
08b668a1c4 MachineModuleInfo: Initialize DbgInfoAvailable depending on debug_cus existing
Before this patch DbgInfoAvailable was set to true in
DwarfDebug::beginModule() or CodeViewDebug::CodeViewDebug(). This made
MIR testing weird since passes would suddenly stop dealing with debug
info just because we stopped the pipeline before the debug printers.

This patch changes the logic to initialize DbgInfoAvailable based on the
fact that debug_compile_units exist in the llvm Module. The debug
printers may then override it with false in case of debug printing being
disabled.

Differential Revision: https://reviews.llvm.org/D53885

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345740 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 17:18:41 +00:00
David Bolvansky
125c8f987d [DAGCombiner] Fold 0 div/rem X to 0
Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover

Reviewed By: RKSimon

Subscribers: craig.topper, llvm-commits

Differential Revision: https://reviews.llvm.org/D52504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345721 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 14:18:57 +00:00