Commit Graph

56 Commits

Author SHA1 Message Date
Matt Arsenault
d2643e2ff9 AMDGPU: Add MachineInstr overloads for instruction format tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250797 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 04:35:43 +00:00
Matt Arsenault
3f7c35a966 AMDGPU: Use explicit register size indirect pseudos
This stops using an unknown reg class operand.

Currently build_vector selection has a broken looking check
where it tries to use a VGPR reg class and an SGPR one if it
sees an SGPR use.

With the source operand has an explicit VGPR class,
illegal copies will be inserted that SIFixSGPRCopies will take care
of normally later, which will allow removing the weird check
of build_vector users. Without this, when removed v_movrels_b32 would
still be emitted even though all of the values were only stored in
SGPRs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249494 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-07 00:42:51 +00:00
Matt Arsenault
7a6a7f2409 AMDGPU: Fix recomputing dominator tree unnecessarily
SIFixSGPRCopies does not modify the CFG, but this was
being recomputed before running SIFoldOperands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248587 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-25 17:21:28 +00:00
Matt Arsenault
d3ff1cd1f5 AMDGPU/SI: Remove VCCReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244380 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-08 00:41:48 +00:00
Matt Arsenault
e601cbe15d AMDGPU/SI: Remove EXECReg
For the same reasons as the other physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244062 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-05 16:42:57 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00