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Author	SHA1	Message	Date
Lama Saba	2ee7806ef3	[X86] Replace slow LEA instructions in X86 According to Intel's Optimization Reference Manual for SNB+: " For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must dispatch via port 1: - LEA that has all three source operands: base, index, and offset - LEA that uses base and index registers where the base is EBP, RBP,or R13 - LEA that uses RIP relative addressing mode - LEA that uses 16-bit addressing mode " This patch currently handles the first 2 cases only. Differential Revision: https://reviews.llvm.org/D32277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303333 91177308-0d34-0410-b5e6-96231b3b80d8	2017-05-18 08:11:50 +00:00
Reid Kleckner	c4cdac05ab	Revert "[X86] Replace slow LEA instructions in X86" This reverts commit r303183, it broke various buildbots and introduced sanitizer errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303199 91177308-0d34-0410-b5e6-96231b3b80d8	2017-05-16 19:55:03 +00:00
Lama Saba	371c802090	[X86] Replace slow LEA instructions in X86 According to Intel's Optimization Reference Manual for SNB+: " For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must dispatch via port 1: - LEA that has all three source operands: base, index, and offset - LEA that uses base and index registers where the base is EBP, RBP,or R13 - LEA that uses RIP relative addressing mode - LEA that uses 16-bit addressing mode " This patch currently handles the first 2 cases only. Differential Revision: https://reviews.llvm.org/D32277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303183 91177308-0d34-0410-b5e6-96231b3b80d8	2017-05-16 16:01:36 +00:00

Author

SHA1

Message

Date

Lama Saba

2ee7806ef3

[X86] Replace slow LEA instructions in X86

According to Intel's Optimization Reference Manual for SNB+:
  " For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must
    dispatch via port 1:
  - LEA that has all three source operands: base, index, and offset
  - LEA that uses base and index registers where the base is EBP, RBP,or R13
  - LEA that uses RIP relative addressing mode
  - LEA that uses 16-bit addressing mode "
  This patch currently handles the first 2 cases only.
 
Differential Revision: https://reviews.llvm.org/D32277



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303333 91177308-0d34-0410-b5e6-96231b3b80d8

2017-05-18 08:11:50 +00:00

Reid Kleckner

c4cdac05ab

Revert "[X86] Replace slow LEA instructions in X86"

This reverts commit r303183, it broke various buildbots and introduced
sanitizer errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303199 91177308-0d34-0410-b5e6-96231b3b80d8

2017-05-16 19:55:03 +00:00

Lama Saba

371c802090

[X86] Replace slow LEA instructions in X86

According to Intel's Optimization Reference Manual for SNB+:
  " For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must
    dispatch via port 1:
  - LEA that has all three source operands: base, index, and offset
  - LEA that uses base and index registers where the base is EBP, RBP,or R13
  - LEA that uses RIP relative addressing mode
  - LEA that uses 16-bit addressing mode "
  This patch currently handles the first 2 cases only.
 
Differential Revision: https://reviews.llvm.org/D32277



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303183 91177308-0d34-0410-b5e6-96231b3b80d8

2017-05-16 16:01:36 +00:00

3 Commits