Commit Graph

7 Commits

Author SHA1 Message Date
Matt Arsenault
d706d030af AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
Currently the default C calling convention functions are treated
the same as compute kernels. Make this explicit so the default
calling convention can be changed to a non-kernel.

Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'
on the relevant test directories (and undoing in one place that actually
wanted a non-kernel).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298444 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 21:39:51 +00:00
Justin Lebar
600740bf18 [LSV] Use the original loads' names for the extractelement instructions.
Summary:
LSV replaces multiple adjacent loads with one vectorized load and a
bunch of extractelement instructions.  This patch makes the
extractelement instructions' names match those of the original loads,
for (hopefully) improved readability.

Reviewers: asbirlea, tstellarAMD

Subscribers: arsenm, mzolotukhin

Differential Revision: https://reviews.llvm.org/D23748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280818 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-07 15:49:48 +00:00
Alina Sbirlea
87c883dc04 Add TLI.allowsMisalignedMemoryAccesses to LoadStoreVectorizer
Summary: Extend TTI to access TLI.allowsMisalignedMemoryAccesses(). Check condition when vectorizing load and store chains.
Add additional parameters: AddressSpace, Alignment, Fast.

Reviewers: llvm-commits, jlebar

Subscribers: arsenm, mzolotukhin

Differential Revision: http://reviews.llvm.org/D21935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275100 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-11 20:46:17 +00:00
Matt Arsenault
2623a06878 LoadStoreVectorizer: Don't increase alignment with no align set
If no alignment was set on the load/stores, it would vectorize
to the new type even though this increases the default alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274323 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-01 02:09:38 +00:00
Matt Arsenault
d8f310cdf9 LoadStoreVectorizer: Check TTI for vec reg bit width
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274322 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-01 02:07:22 +00:00
Matt Arsenault
378e1693a1 LoadStoreVectorizer: if one element of a vector is integer, default to
integer.

Fixes issues on some architectures where we use arithmetic ops to build
vectors, which can cause bad things to happen for loads/stores of mixed
types.

Patch by Fiona Glaser

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274307 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-01 00:37:01 +00:00
Matt Arsenault
8b86030deb Add LoadStoreVectorizer pass
This was contributed by Apple, and I've been working on
minimal cleanups and generalizing it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274293 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-30 23:11:38 +00:00