Commit Graph

2102 Commits

Author SHA1 Message Date
Roman Lebedev
00258393d4 [MCA][NFC] Add generic XOP resource tests
Summary:
Based on
* [[ https://support.amd.com/TechDocs/43479.pdf | AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions ]],
* [[ https://support.amd.com/TechDocs/24594.pdf | AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions]],
* https://en.wikipedia.org/wiki/XOP_instruction_set

Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.

Reviewers: RKSimon, craig.topper, andreadb, spatel

Reviewed By: RKSimon

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D48264

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335034 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 09:21:27 +00:00
Roman Lebedev
857083aa70 [MCA][NFC] Add generic TBM resource tests
Summary:
Based on https://support.amd.com/TechDocs/24594.pdf,
https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)

Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.

Reviewers: RKSimon, craig.topper, simark, andreadb

Reviewed By: RKSimon

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D48252

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335033 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 09:21:22 +00:00
Andrea Di Biagio
c75619bff7 [llvm-mca] Use an ordered map to collect hardware statistics. NFC.
Histogram entries are now ordered by key.  This should improves their
readability when statistics are printed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334961 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-18 17:04:56 +00:00
Andrea Di Biagio
0f51d6d4e9 [llvm-mca] Add tests for XOP and AVX512 instructions that implicitly clear the upper portion of a super-register.
When the destination register of a XOP instruction is an XMM register, bits
[255:128] of the corresponding YMM register are cleared.

When the destination register of a EVEX encoded instruction is an XMM/YMM
register, the upper bits of the corresponding ZMM are cleared.
On processors that feature AVX512, a write to an XMM registers always clears the
upper portion of the corresponding ZMM register if the instruction is VEX or
EVEX encoded.

These new tests show some interesting cases which aren't correctly analyzed by
llvm-mca. The lack of knowledge related to the implicit update on the
super-registers is addressed by D48225.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334945 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-18 14:00:30 +00:00
Clement Courbet
637504b217 [X86] Fix NOOP sched overrides on BDW/HSW/SKL.
Summary: Noop certainly does not use resources.

Reviewers: RKSimon, craig.topper, andreadb

Subscribers: gbedwell, llvm-commits, gchatelet

Differential Revision: https://reviews.llvm.org/D48028

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334927 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-18 06:48:22 +00:00
Simon Pilgrim
a9e397149a [llvm-mca][X86] Add some avx512f/avx512vl resource test placeholders
There are a lot of instructions to add under these ISAs (and the other AVX512 variants) but this should demonstrate how to test for the EVEX instructions with different maskings

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334907 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-17 16:25:48 +00:00
Simon Pilgrim
a292a77493 [llvm-mca][x86] Add Generic cpu resource tests
Added a Generic x86 cpu set of resource tests to allow us to check all ISAs.

We currently use SandyBridge as our generic CPU model, but it's better if we actually duplicate these tests for if/when we change the model, it also means we don't end up polluting the SandyBridge folder with tests for ISAs it doesn't support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334853 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-15 18:35:25 +00:00
Roman Lebedev
6fe55f4897 [MCA] Add -summary-view option
Summary:
While that is indeed a quite interesting summary stat,
there are cases where it does not really add anything
other than consuming extra lines.

Declutters the output of D48190.

Reviewers: RKSimon, andreadb, courbet, craig.topper

Reviewed By: andreadb

Subscribers: javed.absar, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D48209

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334833 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-15 14:01:43 +00:00
Roman Lebedev
cedc64e771 [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats
Summary:
There does not seem to be any other tests for this.
Split off from D47676.

Reviewers: RKSimon, craig.topper, courbet, andreadb

Reviewed By: andreadb

Subscribers: javed.absar, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D48190

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334832 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-15 14:01:35 +00:00
Andrea Di Biagio
8fc6007820 [llvm-mca] Add tests for instructions that implicitly clear the upper portion of a super-register.
On x86-64, a write to register EAX implicitly clears the upper half or RAX.
128-bit AVX instructions clear the upper 128-bit of the YMM register that
aliases the XMM definition register.

llvm-mca doesn't know about register writes that implicitly clear the upper
portion of an aliasing super-register. This issue will be fixed in a future patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334742 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-14 17:48:42 +00:00
Andrea Di Biagio
c8cb969dd3 [llvm-mca] Add another test for partial register stalls.
This test checks that a physical register is correctly allocated for the partial
write to register BX.
The ADD instruction has to wait for the write to RBX (and BX) before being
executed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334730 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-14 15:54:34 +00:00
Andrea Di Biagio
2a8508d8ca [llvm-mca] Fixed a bug in the logic that checks if a memory operation is ready to execute.
Fixes PR37790.

In some (very rare) cases, the LSUnit (Load/Store unit) was wrongly marking a
load (or store) as "ready to execute" effectively bypassing older memory barrier
instructions.

To reproduce this bug, the memory barrier must be the first instruction in the
input assembly sequence, and it doesn't have to perform any register writes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334633 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-13 18:30:14 +00:00
Pavel Labath
c271b02f29 [DWARF/AccelTable] Remove getDIESectionOffset for DWARF v5 entries
Summary:
This method was not correct for entries in DWO files as it assumed it
could just add up the CU and DIE offsets to get the absolute DIE offset.
This is not correct for the DWO files, as here the CU offset will
reference the skeleton unit, whereas the DIE offset will be the offset
in the full unit in the DWO file.

Unfortunately, this means that we are not able to determine the absolute
DIE offset using the information in the .debug_names section alone,
which means we have to offload some of this work to the users of this
class.

To demonstrate how this can be done, I've added/fixed the ability to
lookup entries using accelerator tables in DWO files in llvm-dwarfdump.
To make this happen, I've needed to make two extra changes in other
classes:
- made the DWARFContext method to lookup a CU based on the section
  offset public. I've needed this functionality to lookup a CU, and this
  seems like a useful thing in general.
- made DWARFUnit::getDWOId call extractDIEsIfNeeded. Before this, the
  DWOId was filled in only if the root DIE happened to be parsed
  before we called the accessor. Since the lazy parsing is supposed to
  happen under the hood, calling extractDIEsIfNeeded seems appropriate.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D48009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334578 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-13 08:14:27 +00:00
Clement Courbet
ca4e522508 [X86] Fix skylake server scheduling info.
Summary:
This fixes most of the scheduling info for SKX vector operations.
I had to split a lot of the YMM/ZMM classes into separate classes for YMM and ZMM.

The before/after llvm-exegesis analysis are in the phabricator diff.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47721

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334407 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-11 14:37:53 +00:00
Simon Pilgrim
63f4875014 [X86][BtVer2] Add support for all SUB/XOR 32/64 scalar instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), these instructions are dependency breaking and fast-path zero the destination register (and appropriate EFLAGS bits).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334303 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-08 17:00:45 +00:00
Simon Pilgrim
21448274b7 [X86][BtVer2] Remove SBB tests that were accidentally added in rL334296
These aren't true zero-idiom instructions (just dependency breaking).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334297 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-08 15:43:00 +00:00
Simon Pilgrim
0197608901 [X86][BtVer2] Add tests for scalar SUB/XOR instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334296 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-08 15:28:43 +00:00
Simon Pilgrim
9d5c29c225 [X86][BtVer2] Limit zero idiom tests to a single iteration.
Reduces output size and we're only wanting to check that the instructions are fast-path'd (just Dispatch+Retire) anyhow

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334292 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-08 15:01:40 +00:00
Paul Semel
f36d22b003 [llvm-strip] Expose --strip-unneeded option
Differential Revision: https://reviews.llvm.org/D47818

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334182 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-07 10:05:25 +00:00
Peter Collingbourne
032b3051e3 llvm-readobj: fix printing number of relocations in Android packed format.
With '-elf-output-style=GNU -relocations', a header containing the number
of entries is printed before all the relocation entries in the section.
For Android packed format, we need to perform the unpacking first before
we can get the actual number of relocations in the section.

Patch by Rahul Chaudhry!

Differential Revision: https://reviews.llvm.org/D47800

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334147 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-07 00:02:07 +00:00
Alexander Shaposhnikov
ad593b0363 [llvm-strip] Expose --discard-all option
Expose objcopy's --discard-all option in llvm-strip.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47750


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334131 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-06 21:23:19 +00:00
Simon Pilgrim
04c4197451 [X86][BtVer2] Add support for all vector instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334119 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-06 19:06:09 +00:00
Simon Pilgrim
feaa0dca1c [llvm-mca][x86] Fix all resources-x86_64.s tests to use different registers in reg-reg cases
I noticed while working on zero-idiom + dependency-breaking support (PR36671) that most of our binary instruction tests were reusing the same src registers, which would cause the tests to fail once we enable scalar zero-idiom support on btver2. Fixed in all targets to keep them in sync.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334110 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-06 18:20:25 +00:00
Simon Pilgrim
a0a79b9927 [X86][BtVer2] Add tests for all vector instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.

TODO: Scalar instructions still need to be tested (need to check EFLAGS handling).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334104 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-06 16:14:37 +00:00
Sanjay Patel
863443f97f [CodeGen] assume max/default throughput for unspecified instructions
This is a fix for the problem arising in D47374 (PR37678):
https://bugs.llvm.org/show_bug.cgi?id=37678

We may not have throughput info because it's not specified in the model 
or it's not available with variant scheduling, so assume that those
instructions can execute/complete at max-issue-width.

Differential Revision: https://reviews.llvm.org/D47723


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334055 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 23:34:45 +00:00
Andrea Di Biagio
04b507e104 [llvm-mca] Correctly update the CyclesLeft of a register read in the presence of partial register updates.
This patch fixe the logic in ReadState::cycleEvent(). That method was not
correctly updating field `TotalCycles`.

Added extra code comments in class ReadState to better describe each field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334028 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 17:12:02 +00:00
Alexander Shaposhnikov
711621feb7 [llvm-strip] Add missing aliases for --strip-debug
Add missing aliases for --strip-debug: -g, -S, -d.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47674


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333940 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 18:55:41 +00:00
Andrea Di Biagio
47acfadfe7 [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca.
This patch is the last of a sequence of three patches related to LLVM-dev RFC
"MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html

This fixes PR36672.

The main goal of this patch is to teach llvm-mca how to solve variant scheduling
classes.  This patch does that, plus it adds new variant scheduling classes to
the BtVer2 scheduling model to identify so-called zero-idioms (i.e. so-called
dependency breaking instructions that are known to generate zero, and that are
optimized out in hardware at register renaming stage).

Without the BtVer2 change, this patch would not have had any meaningful tests.
This patch is effectively the union of two changes:
 1) a change that teaches llvm-mca how to resolve variant scheduling classes.
 2) a change to the BtVer2 scheduling model that allows us to special-case
    packed XOR zero-idioms (this partially fixes PR36671).

Differential Revision: https://reviews.llvm.org/D47374 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333909 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 15:43:09 +00:00
Alexander Ivchenko
2db6f82ea7 [llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes in .note.gnu.property
Resubmit of r333424. This version contains the fix for fails found by buildbots
on some targets.

This patch allows parsing GNU_PROPERTY_X86_FEATURE_1_AND
notes in .note.gnu.property sections. These notes
indicate that the object file is built to support Intel CET.

patch by mike.dvoretsky

Differential Revision: https://reviews.llvm.org/D47473



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333908 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 15:14:18 +00:00
Greg Bedwell
feb319a84a [llvm-mca] Regenerate a test to remove a double newline
Command used: py update_mca_test_checks.py ..\test\tools\llvm-mca\*\*.s ..\test\tools\llvm-mca\*\*\*.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333893 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 12:30:03 +00:00
Roman Lebedev
c8a936b18e [llvm-mca] Make sure not to end the test files with an empty line.
Summary:
It's super irritating.

[properly configured] git client then complains about that double-newline,
and you have to use `--force` to ignore the warning, since even if you
fix it manually, it will be reintroduced the very next runtime :/

Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell

Reviewed By: gbedwell

Subscribers: javed.absar, tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D47697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333887 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 11:48:46 +00:00
Paul Semel
64284524f0 [llvm-objcopy] Fix null symbol handling
This fixes the bug where strip-all option was
leading to a malformed outputted ELF file.

Differential Revision: https://reviews.llvm.org/D47414

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333772 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 16:19:46 +00:00
Alexander Shaposhnikov
9eb9307162 [llvm-strip] Add -o option to llvm-strip
This diff implements the option -o 
for specifying a file to write the output to.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47505


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333693 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 20:42:13 +00:00
Clement Courbet
38dac027e1 [X86] Introduce WriteFLDC for x87 constant loads.
Summary:
{FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI} were using WriteMicrocoded.

 - I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
 - For ZnVer1 and Atom, values were transferred form InstRWs.
 - For SLM and BtVer2, I've guessed some values :(

Reviewers: RKSimon, craig.topper, andreadb

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D47585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333656 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 14:22:01 +00:00
Clement Courbet
7f6275200a [X86] Extract latency of fldz/fld1 in separate classes.
Summary:
 - I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
 - For ZnVer1 and Atom, values were transferred form `InstRW`s.
 - For SLM and BtVer2, values are from Agner.

This is split off from https://reviews.llvm.org/D47377

Reviewers: RKSimon, andreadb

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D47523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333642 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 11:41:27 +00:00
Pavel Labath
2299c2e836 DWARFAcceleratorTable: fix equal_range iterators
Summary:
Both (Apple and DWARF5) implementations of the iterators had bugs which
resulted in crashes if one attempted to iterate through the accelerator
tables all the way.

For the Apple tables, the issue was that we did not clear the DataOffset
field when we reached the end, which made our iterator compare unequal
to the "end" iterator. For the Dwarf5 tables, the problem was that we
incremented the CurrentIndex pointer and then used the incremented
(possibly invalid) pointer to check whether we have reached the end of
the index list.

The reason these bugs went undetected is because their only user
(dwarfdump) only ever searched for the first match. Besides allowing us
to test this fix, changing llvm-dwarfdump --find to display all matches
seems like a good improvement (it makes the behavior consistent with the
--name option), so I change llvm-dwarfdump to do that.

The existing tests would be sufficient to test this fix with the new
llvm-dwarfdump behavior, but I add a special test that demonstrates that
the tool indeed displays multiple results. The find.test test needed to
be tweaked a bit as the tool now does not print the ".debug_info
contents" header (also consistent with how --name works).

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D47543

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333635 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 08:47:00 +00:00
Vedant Kumar
db0f0aca36 [llvm-cov] Use the new PrintHTMLEscaped utility
This removes some duplicate logic to escape characters in HTML output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333608 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-30 23:35:14 +00:00
Peter Collingbourne
44e7cf45f6 llvm-objcopy: Set sh_link to 0 on unrecognized symtab-linked sections.
Per discussion on the generic-abi mailing list:
https://groups.google.com/forum/#!topic/generic-abi/MPr8TVtnVn4

An object file manipulation tool must either write out a symbol
table with the same number of entries as the original symbol table
and in the same order, or if this is impossible, refuse to operate
on the object file if it has unrecognized sections that are linked
to the symtab section. However, existing tools (namely GNU strip,
GNU objcopy and ld.{bfd,gold,lld} -r) do not comply with this at
present: they change symbol table indexes and set sh_link to 0 on
the unrecognized symtab-linked sections.

We intend to use the latter as a (temporary) signal that a tool has
operated on a proposed new symtab-linked section and invalidated the
symbol table indexes. However, llvm-objcopy currently keeps sh_link
pointing to the new symtab section. This patch changes llvm-objcopy
to set sh_link to 0 to match the behaviour of the other tools.

Differential Revision: https://reviews.llvm.org/D47404

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333581 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-30 19:30:39 +00:00
Galina Kistanova
80f62ff390 Reverted r333424 as it broke multiple build bots and left unfixed for a long time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333578 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-30 18:51:08 +00:00
Jonas Devlieghere
e22dca5286 [dsymutil] Escape HTML special characters in plist.
When printing string in the Plist, we weren't escaping the characters
which lead to invalid XML. This patch adds the escape logic to
StringExtras.

rdar://39785334

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333565 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-30 17:47:11 +00:00
Alexander Ivchenko
980b901b1e [llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes in .note.gnu.property
This patch allows parsing GNU_PROPERTY_X86_FEATURE_1_AND
notes in .note.gnu.property sections. These notes
indicate that the object file is built to support Intel CET.

patch by mike.dvoretsky

Differential Revision: https://reviews.llvm.org/D47473



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333424 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 14:49:51 +00:00
Clement Courbet
6cb2dcb661 [X86][Sched] Add InstRW for CLC on Intel after SNB.
Summary:
After SNB, Intel CPUs can rename CF independently of other EFLAGS,
so the renamer can zero it for free. Note that STC still consumes resources.

To reproduce: `$ llvm-exegesis -mode=uops -opcode-name=CLC`

On SNB:
```
---
key:
  opcode_name:     CLC
  mode:            uops
  config:          ''
cpu_name:        sandybridge
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: '3', value: 0.0014, debug_string: SBPort0 }
  - { key: '4', value: 0.0013, debug_string: SBPort1 }
  - { key: '5', value: 0.0003, debug_string: SBPort4 }
  - { key: '6', value: 0.0029, debug_string: SBPort5 }
  - { key: '10', value: 0.0003, debug_string: SBPort23 }
error:           ''
info:            'instruction is serial, repeating a random one.
Snippet:
CLC
'
...
```

On HSW:
```
---
key:
  opcode_name:     CLC
  mode:            uops
  config:          ''
cpu_name:        haswell
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: '3', value: 0.001, debug_string: HWPort0 }
  - { key: '4', value: 0.0009, debug_string: HWPort1 }
  - { key: '5', value: 0.0004, debug_string: HWPort2 }
  - { key: '6', value: 0.0006, debug_string: HWPort3 }
  - { key: '7', value: 0.0002, debug_string: HWPort4 }
  - { key: '8', value: 0.0012, debug_string: HWPort5 }
  - { key: '9', value: 0.0022, debug_string: HWPort6 }
  - { key: '10', value: 0.0001, debug_string: HWPort7 }
error:           ''
info:            'instruction is serial, repeating a random one.
Snippet:
CLC
'
...

```

Reviewers: craig.topper, RKSimon

Subscribers: gchatelet, llvm-commits

Differential Revision: https://reviews.llvm.org/D47362

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333392 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 06:19:39 +00:00
Jonas Devlieghere
98ac263943 [dwarfdump] Make -c and -p work together
When requesting to dump both the parent chain and children, we used to
print the DIE more than once because we propagated the dump options to
the parent without clearing the respective flags. This commit fixes this
oversight and adds a test.

rdar://39415292

Differential revision: https://reviews.llvm.org/D47263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333350 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-26 19:39:56 +00:00
Paul Semel
5af80c626e [llvm-objcopy] Add --keep-file-symbols option
This option prevent from removing file symbols while removing symbols.

Differential Revision: https://reviews.llvm.org/D46830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333339 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-26 08:10:37 +00:00
Simon Pilgrim
10826be2a6 [X86][SNB] Fix differences between vex/non-vex XMM vector moves (PR37286)
As confirmed by llvm-exegesis, there is no scheduler difference between MOVDQA/MOVDQU and VMOVDQA/VMOVDQU xmm reg-reg moves

Another chapter in the never ending crusade to remove useless InstRW overrides from the x86 scheduler models......

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333271 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-25 12:18:11 +00:00
Paul Semel
fe9deeb432 [llvm-objcopy] Add --strip-unneeded option
Differential Revision: https://reviews.llvm.org/D46896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333267 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-25 11:01:25 +00:00
Greg Bedwell
add59cbbbb [UpdateTestChecks] Improved update_mca_test_checks block analysis
Previously update_mca_test_checks worked entirely at "block" level where
a block is some sequence of lines delimited by at least one empty line.
This generally worked well, but could sometimes lead to excessive
repetition of check lines for various prefixes if some block was almost
identical between prefixes, but not quite (for example, due to a
different dispatch width in the otherwise identical summary views).

This new analyis attempts to split blocks further in the case where the
following conditions are met:
  a) There is some prefix common to every RUN line (typically 'ALL').
  b) The first line of the block is common to the output with every prefix.
  c) The block has the same number of lines for the output with every prefix.

Also, regenerated all llvm-mca test files with the following command:
update_mca_test_checks.py "../test/tools/llvm-mca/*/*.s" "../test/tools/llvm-mca/*/*/*.s"

The new analysis showed a "multiple lines not disambiguated by prefixes" warning
for test "AArch64/Exynos/scheduler-queue-usage.s" so I've also added some
explicit prefixes to each of the RUN lines in that test.

Differential Revision: https://reviews.llvm.org/D47321

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333204 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-24 16:36:44 +00:00
Jonas Devlieghere
2071b7a8b2 [Support] Add color cl category.
This commit adds a color category so tools can document this option and
enables it for dwarfdump and dsymuttil.

rdar://problem/40498996

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333176 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-24 11:36:57 +00:00
Alexander Shaposhnikov
0390dacdd0 [llvm-strip] Minor fix of the usage of TableGen
This is a small follow-up to the revisions r333117 and r331663.

1. Avoid the name conflicts of the generated variables for prefixes.
2. Apply clang-format -i -style=llvm to llvm-objcopy.cpp once again.
3. Add a test for the flag with double dash.

Test plan: make check-all


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333120 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-23 20:39:52 +00:00
Alexander Shaposhnikov
49011d2b65 [llvm-strip] Expose --keep-symbol option
Expose --keep-symbol option in llvm-strip.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47222


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333117 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-23 19:44:19 +00:00