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30212561a1
The new names for FPRs ensure that the Register values within the same class are enumerated consecutively (the order is determined by the `LessRecordRegister` function object). Where there were tables mapping between 32- and 64-bit FPRs (and vice versa) this patch replaces them with Register arithmetic. The enumeration order between different register classes is expected to continue to be arbitrary, although it does impact the conversion from the (overloaded) asm FPR names to Register values, and therefore might require updates to the target if the sorting algorithm is changed. Static asserts were added to ensure that changes to the ordering that would impact the current implementation are detected. Differential Revision: https://reviews.llvm.org/D67423 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373096 91177308-0d34-0410-b5e6-96231b3b80d8
362 lines
14 KiB
C++
362 lines
14 KiB
C++
//===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVDisassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "Utils/RISCVBaseInfo.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class RISCVDisassembler : public MCDisassembler {
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public:
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RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createRISCVDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new RISCVDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeRISCVDisassembler() {
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// Register the disassembler for each target.
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TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
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createRISCVDisassembler);
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TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
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createRISCVDisassembler);
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}
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static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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const FeatureBitset &FeatureBits =
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static_cast<const MCDisassembler *>(Decoder)
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->getSubtargetInfo()
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.getFeatureBits();
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bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
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if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
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return MCDisassembler::Fail;
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Register Reg = RISCV::X0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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Register Reg = RISCV::F0_F + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 8) {
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return MCDisassembler::Fail;
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}
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Register Reg = RISCV::F8_F + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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Register Reg = RISCV::F0_D + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 8) {
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return MCDisassembler::Fail;
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}
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Register Reg = RISCV::F8_D + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo == 0) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo == 2) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 8)
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return MCDisassembler::Fail;
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Register Reg = RISCV::X8 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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// Add implied SP operand for instructions *SP compressed instructions. The SP
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// operand isn't explicitly encoded in the instruction.
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static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
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if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
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Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
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Inst.getOpcode() == RISCV::C_FLWSP ||
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Inst.getOpcode() == RISCV::C_FSWSP ||
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Inst.getOpcode() == RISCV::C_FLDSP ||
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Inst.getOpcode() == RISCV::C_FSDSP ||
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Inst.getOpcode() == RISCV::C_ADDI4SPN) {
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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}
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if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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}
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}
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template <unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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addImplySP(Inst, Address, Decoder);
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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if (Imm == 0)
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return MCDisassembler::Fail;
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return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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addImplySP(Inst, Address, Decoder);
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// Sign-extend the number in the bottom N bits of Imm
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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if (Imm == 0)
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return MCDisassembler::Fail;
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return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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// Sign-extend the number in the bottom N bits of Imm after accounting for
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// the fact that the N bit immediate is stored in N-1 bits (the LSB is
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// always zero)
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<6>(Imm) && "Invalid immediate");
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if (Imm > 31) {
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Imm = (SignExtend64<6>(Imm) & 0xfffff);
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}
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<3>(Imm) && "Invalid immediate");
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if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "RISCVGenDisassemblerTables.inc"
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static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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uint64_t SImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
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uint64_t SImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
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Inst.addOperand(Inst.getOperand(0));
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uint64_t UImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rd = fieldFromInstruction(Insn, 7, 5);
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unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
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DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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unsigned Rd = fieldFromInstruction(Insn, 7, 5);
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unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
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DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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Inst.addOperand(Inst.getOperand(0));
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DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
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return MCDisassembler::Success;
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}
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DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &OS,
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raw_ostream &CS) const {
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// TODO: This will need modification when supporting instruction set
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// extensions with instructions > 32-bits (up to 176 bits wide).
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uint32_t Insn;
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DecodeStatus Result;
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// It's a 32 bit instruction if bit 0 and 1 are 1.
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if ((Bytes[0] & 0x3) == 0x3) {
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Insn = support::endian::read32le(Bytes.data());
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LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
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Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
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Size = 4;
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} else {
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if (Bytes.size() < 2) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Insn = support::endian::read16le(Bytes.data());
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if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
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LLVM_DEBUG(
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dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 2;
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return Result;
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}
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}
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LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
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Size = 2;
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}
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return Result;
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}
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