Petar Avramovic e6fb6db568 [MIParser] Set RegClassOrRegBank during instruction parsing ...

MachineRegisterInfo::createGenericVirtualRegister sets
RegClassOrRegBank to static_cast<RegisterBank *>(nullptr).
MIParser on the other hand doesn't. When we attempt to constrain
Register Class on such VReg, additional COPY is generated.
This way we avoid COPY instructions showing in test that have MIR
input while they are not present with llvm-ir input that was used
to create given MIR for a -run-pass test.

Differential Revision: https://reviews.llvm.org/D68946


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375502 91177308-0d34-0410-b5e6-96231b3b80d8

2019-10-22 14:25:37 +00:00

..

AArch64

[GISel][CombinerHelper] Add a combine turning shuffle_vector into concat_vectors

2019-10-21 20:39:58 +00:00

AMDGPU

AMDGPU/GlobalISel: Legalize fast unsafe FDIV

2019-10-21 22:18:26 +00:00

ARC

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ARM

[ARM] Extra qdadd patterns

2019-10-21 14:06:49 +00:00

AVR

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BPF

[BPF] fix indirect call assembly code

2019-10-21 03:22:03 +00:00

Generic

Reapply r374743 with a fix for the ocaml binding

2019-10-14 16:15:14 +00:00

Hexagon

[DFAPacketizer] Use DFAEmitter. NFC.

2019-10-17 08:34:29 +00:00

Inputs

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Lanai

[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing

2019-09-11 11:16:48 +00:00

Mips

[MIParser] Set RegClassOrRegBank during instruction parsing

2019-10-22 14:25:37 +00:00

MIR

[MIParser] Set RegClassOrRegBank during instruction parsing

2019-10-22 14:25:37 +00:00

MSP430

[TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2)

2019-10-19 16:57:02 +00:00

NVPTX

[NVPTX] Restructure shfl instrinsics and add variants that return a predicate.

2019-10-14 16:53:34 +00:00

PowerPC

[PowerPC] Turn on CR-Logical reducer pass

2019-10-22 12:20:38 +00:00

RISCV

[RISCV] Add MachineInstr immediate verification

2019-10-16 15:06:02 +00:00

SPARC

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SystemZ

[FPEnv] Strict FP tests should use the requisite function attributes.

2019-10-04 17:03:46 +00:00

Thumb

(Re)generate various tests. NFC

2019-10-08 16:16:26 +00:00

Thumb2

[ARM][MVE] Enable truncating masked stores

2019-10-17 12:11:18 +00:00

WebAssembly

[WebAssembly] Allow multivalue signatures in object files

2019-10-18 20:27:30 +00:00

WinCFGuard

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WinEH

[Windows] Replace TrapUnreachable with an int3 insertion pass

2019-09-09 23:04:25 +00:00

X86

[X86][SSE] Add OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1))) -> MOVMSK+CMP reduction combine

2019-10-21 22:36:31 +00:00

XCore

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