Matt Arsenault 4710131927 MIR: Freeze reserved regs after parsing everything ...

The AMDGPU implementation of getReservedRegs depends on
MachineFunctionInfo fields that are parsed from the YAML section. This
was reserving the wrong register since it was setting the reserved
regs before parsing the correct one.

Some tests were relying on the default reserved set for the assumed
default calling convention.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357083 91177308-0d34-0410-b5e6-96231b3b80d8

2019-03-27 16:12:26 +00:00

..

CMakeLists.txt

[CMake] NFC. Updating CMake dependency specifications

2016-11-17 04:36:50 +00:00

LLVMBuild.txt

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00

MILexer.cpp

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00

MILexer.h

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00

MIParser.cpp

MIR: Allow targets to serialize MachineFunctionInfo

2019-03-14 22:54:43 +00:00

MIRParser.cpp

MIR: Freeze reserved regs after parsing everything

2019-03-27 16:12:26 +00:00