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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351636 91177308-0d34-0410-b5e6-96231b3b80d8
785 lines
29 KiB
C++
785 lines
29 KiB
C++
//===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file is part of the XCore Disassembler.
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///
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//===----------------------------------------------------------------------===//
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#include "XCore.h"
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#include "XCoreRegisterInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "xcore-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// A disassembler class for XCore.
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class XCoreDisassembler : public MCDisassembler {
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public:
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XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
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MCDisassembler(STI, Ctx) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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}
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static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint16_t &Insn) {
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// We want to read exactly 2 Bytes of data.
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if (Bytes.size() < 2) {
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Size = 0;
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return false;
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}
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// Encoded as a little-endian 16-bit word in the stream.
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Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
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return true;
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}
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static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn) {
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// We want to read exactly 4 Bytes of data.
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if (Bytes.size() < 4) {
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Size = 0;
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return false;
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}
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// Encoded as a little-endian 32-bit word in the stream.
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Insn =
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(Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
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return true;
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}
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static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
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const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
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const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
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return *(RegInfo->getRegClass(RC).begin() + RegNo);
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}
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode2RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode3RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 11)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 15)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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if (Val > 11)
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return MCDisassembler::Fail;
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static const unsigned Values[] = {
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32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
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};
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Inst.addOperand(MCOperand::createImm(Values[Val]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
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unsigned Combined = fieldFromInstruction(Insn, 6, 5);
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if (Combined < 27)
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return MCDisassembler::Fail;
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if (fieldFromInstruction(Insn, 5, 1)) {
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if (Combined == 31)
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return MCDisassembler::Fail;
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Combined += 5;
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}
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Combined -= 27;
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unsigned Op1High = Combined % 3;
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unsigned Op2High = Combined / 3;
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Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
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Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
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unsigned &Op3) {
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unsigned Combined = fieldFromInstruction(Insn, 6, 5);
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if (Combined >= 27)
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return MCDisassembler::Fail;
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unsigned Op1High = Combined % 3;
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unsigned Op2High = (Combined / 3) % 3;
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unsigned Op3High = Combined / 9;
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Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
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Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
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Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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// Try and decode as a 3R instruction.
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unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
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switch (Opcode) {
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case 0x0:
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Inst.setOpcode(XCore::STW_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x1:
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Inst.setOpcode(XCore::LDW_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x2:
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Inst.setOpcode(XCore::ADD_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x3:
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Inst.setOpcode(XCore::SUB_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x4:
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Inst.setOpcode(XCore::SHL_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x5:
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Inst.setOpcode(XCore::SHR_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x6:
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Inst.setOpcode(XCore::EQ_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x7:
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Inst.setOpcode(XCore::AND_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x8:
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Inst.setOpcode(XCore::OR_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x9:
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Inst.setOpcode(XCore::LDW_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x10:
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Inst.setOpcode(XCore::LD16S_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x11:
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Inst.setOpcode(XCore::LD8U_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x12:
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Inst.setOpcode(XCore::ADD_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x13:
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Inst.setOpcode(XCore::SUB_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x14:
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Inst.setOpcode(XCore::SHL_2rus);
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return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
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case 0x15:
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Inst.setOpcode(XCore::SHR_2rus);
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return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
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case 0x16:
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Inst.setOpcode(XCore::EQ_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x17:
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Inst.setOpcode(XCore::TSETR_3r);
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return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
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case 0x18:
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Inst.setOpcode(XCore::LSS_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x19:
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Inst.setOpcode(XCore::LSU_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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}
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return MCDisassembler::Fail;
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}
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static DecodeStatus
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Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus
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Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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Inst.addOperand(MCOperand::createImm(Op1));
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus
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DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus
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Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus
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DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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Inst.addOperand(MCOperand::createImm(Op2));
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return S;
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}
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static DecodeStatus
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DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus
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DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus
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DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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// Try and decode as a L3R / L2RUS instruction.
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unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
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fieldFromInstruction(Insn, 27, 5) << 4;
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switch (Opcode) {
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case 0x0c:
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Inst.setOpcode(XCore::STW_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x1c:
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Inst.setOpcode(XCore::XOR_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x2c:
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Inst.setOpcode(XCore::ASHR_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x3c:
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Inst.setOpcode(XCore::LDAWF_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x4c:
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Inst.setOpcode(XCore::LDAWB_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x5c:
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Inst.setOpcode(XCore::LDA16F_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x6c:
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Inst.setOpcode(XCore::LDA16B_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x7c:
|
|
Inst.setOpcode(XCore::MUL_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x8c:
|
|
Inst.setOpcode(XCore::DIVS_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x9c:
|
|
Inst.setOpcode(XCore::DIVU_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x10c:
|
|
Inst.setOpcode(XCore::ST16_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x11c:
|
|
Inst.setOpcode(XCore::ST8_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x12c:
|
|
Inst.setOpcode(XCore::ASHR_l2rus);
|
|
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x12d:
|
|
Inst.setOpcode(XCore::OUTPW_l2rus);
|
|
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x12e:
|
|
Inst.setOpcode(XCore::INPW_l2rus);
|
|
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x13c:
|
|
Inst.setOpcode(XCore::LDAWF_l2rus);
|
|
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x14c:
|
|
Inst.setOpcode(XCore::LDAWB_l2rus);
|
|
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x15c:
|
|
Inst.setOpcode(XCore::CRC_l3r);
|
|
return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x18c:
|
|
Inst.setOpcode(XCore::REMS_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x19c:
|
|
Inst.setOpcode(XCore::REMU_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
}
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2;
|
|
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
|
|
Op1, Op2);
|
|
if (S != MCDisassembler::Success)
|
|
return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
|
|
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2;
|
|
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
|
|
Op1, Op2);
|
|
if (S != MCDisassembler::Success)
|
|
return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
|
|
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
Inst.addOperand(MCOperand::createImm(Op1));
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
Inst.addOperand(MCOperand::createImm(Op3));
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeBitpOperand(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
Inst.addOperand(MCOperand::createImm(Op3));
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeBitpOperand(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3, Op4, Op5, Op6;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
|
|
if (S != MCDisassembler::Success)
|
|
return S;
|
|
S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
|
|
if (S != MCDisassembler::Success)
|
|
return S;
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
// Try and decode as a L6R instruction.
|
|
Inst.clear();
|
|
unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
|
|
switch (Opcode) {
|
|
case 0x00:
|
|
Inst.setOpcode(XCore::LMUL_l6r);
|
|
return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
|
|
}
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3, Op4, Op5;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
|
|
if (S != MCDisassembler::Success)
|
|
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
|
|
S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
|
|
if (S != MCDisassembler::Success)
|
|
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
|
|
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
}
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Op1, Op2, Op3;
|
|
unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
}
|
|
if (S == MCDisassembler::Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(
|
|
MCInst &instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
|
|
raw_ostream &vStream, raw_ostream &cStream) const {
|
|
uint16_t insn16;
|
|
|
|
if (!readInstruction16(Bytes, Address, Size, insn16)) {
|
|
return Fail;
|
|
}
|
|
|
|
// Calling the auto-generated decoder function.
|
|
DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
|
|
Address, this, STI);
|
|
if (Result != Fail) {
|
|
Size = 2;
|
|
return Result;
|
|
}
|
|
|
|
uint32_t insn32;
|
|
|
|
if (!readInstruction32(Bytes, Address, Size, insn32)) {
|
|
return Fail;
|
|
}
|
|
|
|
// Calling the auto-generated decoder function.
|
|
Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
|
|
if (Result != Fail) {
|
|
Size = 4;
|
|
return Result;
|
|
}
|
|
|
|
return Fail;
|
|
}
|
|
|
|
namespace llvm {
|
|
Target &getTheXCoreTarget();
|
|
}
|
|
|
|
static MCDisassembler *createXCoreDisassembler(const Target &T,
|
|
const MCSubtargetInfo &STI,
|
|
MCContext &Ctx) {
|
|
return new XCoreDisassembler(STI, Ctx);
|
|
}
|
|
|
|
extern "C" void LLVMInitializeXCoreDisassembler() {
|
|
// Register the disassembler.
|
|
TargetRegistry::RegisterMCDisassembler(getTheXCoreTarget(),
|
|
createXCoreDisassembler);
|
|
}
|