Andrea Di Biagio 73ce7fc085 [TargetInstPredicate] Add definition of CheckInvalidRegisterOperand. ...

This should have been part of r337378. I forgot to svn add it before committing
the change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337380 91177308-0d34-0410-b5e6-96231b3b80d8

2018-07-18 11:16:31 +00:00

..

GlobalISel

[globalisel] Update GlobalISel emitter to match new representation of extending loads

2018-05-05 20:53:24 +00:00

CodeGenCWrappers.h

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

GenericOpcodes.td

[GISel]: Add G_ADDRSPACE_CAST Opcode

2018-06-22 20:58:51 +00:00

Target.td

[cfi-verify] Support AArch64.

2018-07-13 15:19:33 +00:00

TargetCallingConv.td

Swift Calling Convention: add swifterror attribute.

2016-04-01 21:41:15 +00:00

TargetInstrPredicate.td

[TargetInstPredicate] Add definition of CheckInvalidRegisterOperand.

2018-07-18 11:16:31 +00:00

TargetIntrinsicInfo.h

GlobalISel: support translation of intrinsic calls.

2016-07-29 22:32:36 +00:00

TargetItinerary.td

[NFC] Fix comment of class InstrStage

2018-02-12 15:02:49 +00:00

TargetLoweringObjectFile.h

Remove \brief commands from doxygen comments.

2018-05-01 15:54:18 +00:00

TargetMachine.h

[CodeGen] Fix inconsistent declaration parameter name

2018-07-16 18:51:40 +00:00

TargetOptions.h

CodeGen: Add a target option for emitting .addrsig directives for all address-significant symbols.

2018-07-17 22:40:08 +00:00

TargetSchedule.td

[llvm-mca][BtVer2] teach how to identify false dependencies on partially written

2018-07-15 11:01:38 +00:00

TargetSelectionDAG.td

[TableGen] Support multi-alternative pattern fragments

2018-07-13 13:18:00 +00:00