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34715e9f75
This matches what MSVC does for alloca() function calls on ARM. Even if MSVC doesn't support VLAs at the language level, it does support the alloca function. On the clang level, both the _alloca() (when emulating MSVC, which is what the alloca() function expands to) and __builtin_alloca() builtin functions, and VLAs, map to the same LLVM IR "alloca" function - so within LLVM they're not distinguishable from each other. Differential Revision: https://reviews.llvm.org/D42292 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323308 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
870 B
LLVM
27 lines
870 B
LLVM
; RUN: llc -O0 -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
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; RUN: llc -O0 -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
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; RUN: llc -O0 -mtriple thumbv7-windows-mingw32 -filetype asm -o - %s | FileCheck %s
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declare arm_aapcs_vfpcc i32 @num_entries()
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define arm_aapcs_vfpcc void @test___builtin_alloca() {
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entry:
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%array = alloca i8*, align 4
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%call = call arm_aapcs_vfpcc i32 @num_entries()
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%mul = mul i32 4, %call
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%0 = alloca i8, i32 %mul
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store i8* %0, i8** %array, align 4
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ret void
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}
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; CHECK: bl num_entries
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; Any register is actually valid here, but turns out we use lr,
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; because we do not have the kill flag on R0.
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; CHECK: mov.w [[R1:lr]], #7
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; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2
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; CHECK: bic [[R0]], [[R0]], #7
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; CHECK: lsrs r4, [[R0]], #2
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; CHECK: bl __chkstk
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; CHECK: sub.w sp, sp, r4
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