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59bf3bda3c
To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330827 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
5.5 KiB
LLVM
218 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IM %s
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define i32 @udiv(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: udiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __udivsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: divu a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = udiv i32 %a, %b
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ret i32 %1
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}
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define i32 @udiv_constant(i32 %a) nounwind {
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; RV32I-LABEL: udiv_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a1, zero, 5
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; RV32I-NEXT: call __udivsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 838861
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; RV32IM-NEXT: addi a1, a1, -819
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; RV32IM-NEXT: mulhu a0, a0, a1
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; RV32IM-NEXT: srli a0, a0, 2
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; RV32IM-NEXT: ret
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%1 = udiv i32 %a, 5
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ret i32 %1
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}
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define i32 @udiv_pow2(i32 %a) nounwind {
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; RV32I-LABEL: udiv_pow2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 3
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv_pow2:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: srli a0, a0, 3
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; RV32IM-NEXT: ret
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%1 = udiv i32 %a, 8
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ret i32 %1
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}
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define i64 @udiv64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: udiv64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __udivdi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv64:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp)
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; RV32IM-NEXT: call __udivdi3
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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%1 = udiv i64 %a, %b
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ret i64 %1
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}
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define i64 @udiv64_constant(i64 %a) nounwind {
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; RV32I-LABEL: udiv64_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a2, zero, 5
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; RV32I-NEXT: mv a3, zero
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; RV32I-NEXT: call __udivdi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: udiv64_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp)
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; RV32IM-NEXT: addi a2, zero, 5
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; RV32IM-NEXT: mv a3, zero
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; RV32IM-NEXT: call __udivdi3
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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%1 = udiv i64 %a, 5
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ret i64 %1
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}
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define i32 @sdiv(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sdiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __divsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: div a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = sdiv i32 %a, %b
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ret i32 %1
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}
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define i32 @sdiv_constant(i32 %a) nounwind {
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; RV32I-LABEL: sdiv_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a1, zero, 5
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; RV32I-NEXT: call __divsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 419430
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; RV32IM-NEXT: addi a1, a1, 1639
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; RV32IM-NEXT: mulh a0, a0, a1
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; RV32IM-NEXT: srli a1, a0, 31
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; RV32IM-NEXT: srai a0, a0, 1
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = sdiv i32 %a, 5
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ret i32 %1
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}
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define i32 @sdiv_pow2(i32 %a) nounwind {
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; RV32I-LABEL: sdiv_pow2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: srli a1, a1, 29
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srai a0, a0, 3
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv_pow2:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: srai a1, a0, 31
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; RV32IM-NEXT: srli a1, a1, 29
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: srai a0, a0, 3
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; RV32IM-NEXT: ret
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%1 = sdiv i32 %a, 8
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ret i32 %1
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}
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define i64 @sdiv64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: sdiv64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __divdi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv64:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp)
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; RV32IM-NEXT: call __divdi3
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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%1 = sdiv i64 %a, %b
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ret i64 %1
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}
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define i64 @sdiv64_constant(i64 %a) nounwind {
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; RV32I-LABEL: sdiv64_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a2, zero, 5
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; RV32I-NEXT: mv a3, zero
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; RV32I-NEXT: call __divdi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: sdiv64_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp)
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; RV32IM-NEXT: addi a2, zero, 5
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; RV32IM-NEXT: mv a3, zero
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; RV32IM-NEXT: call __divdi3
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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%1 = sdiv i64 %a, 5
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ret i64 %1
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}
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