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Roman Tereshin 6bb56ed117 Reapply "[LSV] Refactoring + supporting bitcasts to a type of different size" 
This reapplies commit r337489 reverted by r337541
Additionally, this commit contains a speculative fix to the issue reported in r337541
(the report does not contain an actionable reproducer, just a stack trace)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337606 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-20 20:10:04 +00:00
..
avx512-shuffles
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
GC
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GlobalISel
[GlobalISel][X86_64] Support for G_SITOFP
2018-07-10 16:38:35 +00:00
3addr-16bit.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
3addr-or.ll
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
2018-03-01 22:32:25 +00:00
3dnow-intrinsics.ll
[X86][MMX] Support MMX build vectors to avoid SSE usage (PR29222)
2018-03-11 19:22:13 +00:00
3dnow-schedule.ll
[X86] Add GPR<->XMM Schedule Tags
2018-05-18 17:58:36 +00:00
4char-promote.ll
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2003-08-03-CallArgLiveRanges.ll
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2003-08-23-DeadBlockTest.ll
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2003-11-03-GlobalBool.ll
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2004-02-13-FrameReturnAddress.ll
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2004-02-14-InefficientStackPointer.ll
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2004-02-22-Casts.ll
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2004-03-30-Select-Max.ll
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2004-04-13-FPCMOV-Crash.ll
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2004-06-10-StackifierCrash.ll
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2004-10-08-SelectSetCCFold.ll
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2005-01-17-CycleInDAG.ll
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2005-02-14-IllegalAssembler.ll
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2005-05-08-FPStackifierPHI.ll
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2006-01-19-ISelFoldingBug.ll
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2006-03-01-InstrSchedBug.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
2006-03-02-InstrSchedBug.ll
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2006-04-04-CrossBlockCrash.ll
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2006-04-27-ISelFoldingBug.ll
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2006-05-01-SchedCausingSpills.ll
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2006-05-02-InstrSched1.ll
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2006-05-02-InstrSched2.ll
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2006-05-08-CoalesceSubRegClass.ll
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2006-05-08-InstrSched.ll
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2006-05-11-InstrSched.ll
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2006-05-17-VectorArg.ll
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2006-05-22-FPSetEQ.ll
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2006-05-25-CycleInDAG.ll
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2006-07-10-InlineAsmAConstraint.ll
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2006-07-12-InlineAsmQConstraint.ll
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2006-07-20-InlineAsm.ll
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2006-07-28-AsmPrint-Long-As-Pointer.ll
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2006-07-31-SingleRegClass.ll
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2006-08-07-CycleInDAG.ll
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2006-08-16-CycleInDAG.ll
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2006-08-21-ExtraMovInst.ll
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2006-09-01-CycleInDAG.ll
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2006-10-02-BoolRetCrash.ll
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2006-10-09-CycleInDAG.ll
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2006-10-10-FindModifiedNodeSlotBug.ll
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2006-10-12-CycleInDAG.ll
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2006-10-13-CycleInDAG.ll
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2006-10-19-SwitchUnnecessaryBranching.ll
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2006-11-12-CSRetCC.ll
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2006-11-17-IllegalMove.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
2006-11-27-SelectLegalize.ll
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2006-12-16-InlineAsmCrash.ll
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2006-12-19-IntelSyntax.ll
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2007-01-08-InstrSched.ll
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2007-01-08-X86-64-Pointer.ll
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2007-01-13-StackPtrIndex.ll
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2007-01-29-InlineAsm-ir.ll
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2007-02-04-OrAddrMode.ll
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2007-02-16-BranchFold.ll
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2007-02-19-LiveIntervalAssert.ll
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2007-02-23-DAGCombine-Miscompile.ll
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2007-02-25-FastCCStack.ll
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2007-03-01-SpillerCrash.ll
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2007-03-15-GEP-Idx-Sink.ll
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2007-03-16-InlineAsm.ll
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2007-03-18-LiveIntervalAssert.ll
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2007-03-24-InlineAsmMultiRegConstraint.ll
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2007-03-24-InlineAsmPModifier.ll
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2007-03-24-InlineAsmVectorOp.ll
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2007-03-24-InlineAsmXConstraint.ll
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2007-03-26-CoalescerBug.ll
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2007-04-08-InlineAsmCrash.ll
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2007-04-11-InlineAsmVectorResult.ll
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2007-04-17-LiveIntervalAssert.ll
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2007-04-24-Huge-Stack.ll
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2007-04-24-VectorCrash.ll
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2007-04-27-InlineAsm-IntMemInput.ll
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2007-05-05-Personality.ll
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2007-05-05-VecCastExpand.ll
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2007-05-14-LiveIntervalAssert.ll
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2007-05-15-maskmovq.ll
[X86][MMX] Regenerate MMX MASKMOV test
2018-02-21 16:38:08 +00:00
2007-05-17-ShuffleISelBug.ll
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2007-06-04-X86-64-CtorAsmBugs.ll
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2007-06-28-X86-64-isel.ll
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2007-06-29-DAGCombinerBug.ll
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2007-06-29-VecFPConstantCSEBug.ll
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2007-07-03-GR64ToVR64.ll
[X86] Regenerate GPR:XMM bitcast test
2018-02-21 15:05:47 +00:00
2007-07-10-StackerAssert.ll
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2007-07-18-Vector-Extract.ll
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2007-08-01-LiveVariablesBug.ll
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2007-08-09-IllegalX86-64Asm.ll
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2007-08-10-SignExtSubreg.ll
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2007-09-05-InvalidAsm.ll
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2007-09-06-ExtWeakAliasee.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
2007-09-27-LDIntrinsics.ll
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2007-10-04-AvoidEFLAGSCopy.ll
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2007-10-12-CoalesceExtSubReg.ll
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2007-10-12-SpillerUnfold1.ll
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2007-10-12-SpillerUnfold2.ll
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2007-10-14-CoalescerCrash.ll
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2007-10-15-CoalescerCrash.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2007-10-16-CoalescerCrash.ll
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2007-10-19-SpillerUnfold.ll
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2007-10-28-inlineasm-q-modifier.ll
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2007-10-29-ExtendSetCC.ll
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2007-10-30-LSRCrash.ll
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2007-10-31-extractelement-i64.ll
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2007-11-01-ISelCrash.ll
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2007-11-03-x86-64-q-constraint.ll
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2007-11-04-LiveIntervalCrash.ll
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2007-11-04-LiveVariablesBug.ll
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2007-11-04-rip-immediate-constant.ll
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2007-11-06-InstrSched.ll
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2007-11-07-MulBy4.ll
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2007-11-30-LoadFolding-Bug.ll
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2007-12-16-BURRSchedCrash.ll
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2007-12-18-LoadCSEBug.ll
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2008-01-08-IllegalCMP.ll
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2008-01-08-SchedulerCrash.ll
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2008-01-09-LongDoubleSin.ll
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2008-01-16-FPStackifierAssert.ll
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2008-01-16-InvalidDAGCombineXform.ll
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2008-02-05-ISelCrash.ll
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2008-02-06-LoadFoldingBug.ll
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2008-02-14-BitMiscompile.ll
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2008-02-18-TailMergingBug.ll
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2008-02-20-InlineAsmClobber.ll
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2008-02-22-LocalRegAllocBug.ll
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2008-02-25-InlineAsmBug.ll
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2008-02-25-X86-64-CoalescerBug.ll
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2008-02-26-AsmDirectMemOp.ll
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2008-02-27-DeadSlotElimBug.ll
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2008-02-27-PEICrash.ll
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2008-03-06-frem-fpstack.ll
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2008-03-07-APIntBug.ll
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2008-03-10-RegAllocInfLoop.ll
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2008-03-12-ThreadLocalAlias.ll
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2008-03-13-TwoAddrPassCrash.ll
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2008-03-14-SpillerCrash.ll
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2008-03-19-DAGCombinerBug.ll
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2008-03-23-DarwinAsmComments.ll
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2008-03-25-TwoAddrPassBug.ll
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2008-03-31-SpillerFoldingBug.ll
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2008-04-02-unnamedEH.ll
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2008-04-08-CoalescerCrash.ll
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2008-04-09-BranchFolding.ll
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2008-04-15-LiveVariableBug.ll
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2008-04-16-CoalescerBug.ll
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2008-04-16-ReMatBug.ll
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2008-04-17-CoalescerBug.ll
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2008-04-24-MemCpyBug.ll
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2008-04-24-pblendw-fold-crash.ll
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2008-04-26-Asm-Optimize-Imm.ll
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2008-04-28-CoalescerBug.ll
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2008-04-28-CyclicSchedUnit.ll
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2008-05-01-InvalidOrdCompare.ll
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2008-05-09-PHIElimBug.ll
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2008-05-09-ShuffleLoweringBug.ll
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2008-05-12-tailmerge-5.ll
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2008-05-21-CoalescerBug.ll
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2008-05-22-FoldUnalignedLoad.ll
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2008-05-28-CoalescerBug.ll
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2008-05-28-LocalRegAllocBug.ll
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2008-06-13-NotVolatileLoadStore.ll
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2008-06-13-VolatileLoadStore.ll
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2008-06-16-SubregsBug.ll
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2008-06-25-VecISelBug.ll
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2008-07-07-DanglingDeadInsts.ll
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2008-07-09-ELFSectionAttributes.ll
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2008-07-11-SHLBy1.ll
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2008-07-16-CoalescerCrash.ll
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2008-07-19-movups-spills.ll
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2008-07-22-CombinerCrash.ll
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2008-07-23-VSetCC.ll
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2008-08-06-CmpStride.ll
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2008-08-06-RewriterBug.ll
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2008-08-17-UComiCodeGenBug.ll
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2008-08-23-64Bit-maskmovq.ll
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2008-08-31-EH_RETURN32.ll
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2008-08-31-EH_RETURN64.ll
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2008-09-05-sinttofp-2xi32.ll
[X86][SSE] Regenerate old sitofp v2i32 test
2018-02-10 14:45:58 +00:00
2008-09-09-LinearScanBug.ll
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2008-09-11-CoalescerBug2.ll
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2008-09-11-CoalescerBug.ll
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2008-09-17-inline-asm-1.ll
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2008-09-18-inline-asm-2.ll
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2008-09-19-RegAllocBug.ll
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2008-09-25-sseregparm-1.ll
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2008-09-26-FrameAddrBug.ll
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2008-09-29-ReMatBug.ll
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2008-09-29-VolatileBug.ll
[X86] Switch a test from grep to FileCheck. NFC
2018-04-11 01:05:32 +00:00
2008-10-06-x87ld-nan-1.ll
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2008-10-06-x87ld-nan-2.ll
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2008-10-07-SSEISelBug.ll
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2008-10-11-CallCrash.ll
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2008-10-13-CoalescerBug.ll
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2008-10-16-VecUnaryOp.ll
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2008-10-17-Asm64bitRConstraint.ll
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2008-10-20-AsmDoubleInI32.ll
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2008-10-24-FlippedCompare.ll
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2008-10-27-CoalescerBug.ll
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2008-10-29-ExpandVAARG.ll
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2008-11-03-F80VAARG.ll
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2008-11-06-testb.ll
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2008-11-13-inlineasm-3.ll
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2008-11-29-ULT-Sign.ll
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2008-12-01-loop-iv-used-outside-loop.ll
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2008-12-01-SpillerAssert.ll
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2008-12-02-dagcombine-1.ll
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2008-12-02-dagcombine-2.ll
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2008-12-02-dagcombine-3.ll
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2008-12-02-IllegalResultType.ll
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2008-12-16-dagcombine-4.ll
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2008-12-19-EarlyClobberBug.ll
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2008-12-22-dagcombine-5.ll
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2008-12-23-crazy-address.ll
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2008-12-23-dagcombine-6.ll
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2009-01-13-DoubleUpdate.ll
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2009-01-16-SchedulerBug.ll
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2009-01-16-UIntToFP.ll
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2009-01-18-ConstantExprCrash.ll
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2009-01-25-NoSSE.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2009-01-26-WrongCheck.ll
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2009-01-27-NullStrings.ll
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2009-01-31-BigShift2.ll
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2009-01-31-BigShift3.ll
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2009-01-31-BigShift.ll
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2009-02-01-LargeMask.ll
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2009-02-03-AnalyzedTwice.ll
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2009-02-04-sext-i64-gep.ll
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2009-02-08-CoalescerBug.ll
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2009-02-09-ivs-different-sizes.ll
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2009-02-11-codegenprepare-reuse.ll
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2009-02-12-DebugInfoVLA.ll
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2009-02-12-InlineAsm-nieZ-constraints.ll
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2009-02-12-SpillerBug.ll
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2009-02-21-ExtWeakInitializer.ll
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2009-02-25-CommuteBug.ll
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2009-02-26-MachineLICMBug.ll
[X86] Auto-generate full checks. NFC
2018-02-04 23:48:51 +00:00
2009-03-03-BitcastLongDouble.ll
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2009-03-03-BTHang.ll
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2009-03-05-burr-list-crash.ll
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2009-03-07-FPConstSelect.ll
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2009-03-09-APIntCrash.ll
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2009-03-09-SpillerBug.ll
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2009-03-10-CoalescerBug.ll
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2009-03-12-CPAlignBug.ll
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2009-03-13-PHIElimBug.ll
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2009-03-16-PHIElimInLPad.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
2009-03-23-i80-fp80.ll
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2009-03-23-LinearScanBug.ll
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2009-03-23-MultiUseSched.ll
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2009-03-25-TestBug.ll
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2009-03-26-NoImplicitFPBug.ll
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2009-04-12-FastIselOverflowCrash.ll
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2009-04-12-picrel.ll
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2009-04-13-2AddrAssert-2.ll
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2009-04-13-2AddrAssert.ll
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2009-04-14-IllegalRegs.ll
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2009-04-16-SpillerUnfold.ll
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2009-04-24.ll
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2009-04-25-CoalescerBug.ll
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2009-04-27-CoalescerAssert.ll
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2009-04-27-LiveIntervalsAssert2.ll
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2009-04-27-LiveIntervalsAssert.ll
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2009-04-29-IndirectDestOperands.ll
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2009-04-29-LinearScanBug.ll
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2009-04-29-RegAllocAssert.ll
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2009-04-scale.ll
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2009-05-08-InlineAsmIOffset.ll
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2009-05-11-tailmerge-crash.ll
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2009-05-19-SingleElementExtractElement.ll
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2009-05-23-available_externally.ll
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2009-05-23-dagcombine-shifts.ll
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2009-05-28-DAGCombineCrash.ll
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2009-05-30-ISelBug.ll
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2009-06-02-RewriterBug.ll
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2009-06-03-Win64DisableRedZone.ll
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2009-06-03-Win64SpillXMM.ll
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2009-06-04-VirtualLiveIn.ll
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2009-06-05-sitofpCrash.ll
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2009-06-05-VariableIndexInsert.ll
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2009-06-05-VZextByteShort.ll
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2009-06-06-ConcatVectors.ll
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2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
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2009-06-15-not-a-tail-call.ll
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2009-06-18-movlp-shuffle-register.ll
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2009-07-06-TwoAddrAssert.ll
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2009-07-07-SplitICmp.ll
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2009-07-09-ExtractBoolFromVector.ll
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2009-07-15-CoalescerBug.ll
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2009-07-16-CoalescerBug.ll
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2009-07-19-AsmExtraOperands.ll
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2009-07-20-CoalescerBug.ll
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2009-07-20-DAGCombineBug.ll
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2009-08-06-branchfolder-crash.ll
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2009-08-06-inlineasm.ll
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2009-08-08-CastError.ll
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2009-08-12-badswitch.ll
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2009-08-14-Win64MemoryIndirectArg.ll
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2009-08-19-LoadNarrowingMiscompile.ll
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2009-08-23-SubRegReuseUndo.ll
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2009-09-10-LoadFoldingBug.ll
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2009-09-10-SpillComments.ll
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2009-09-16-CoalescerBug.ll
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2009-09-19-earlyclobber.ll
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2009-09-21-NoSpillLoopCount.ll
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2009-09-22-CoalescerBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-10-14-LiveVariablesBug.ll
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2009-10-16-Scope.ll
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2009-10-19-atomic-cmp-eflags.ll
[X86] Teach DAG unfoldMemoryOperand to reconvert CMPs to tests
2018-02-05 18:58:58 +00:00
2009-10-19-EmergencySpill.ll
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2009-10-25-RewriterBug.ll
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2009-11-04-SubregCoalescingBug.ll
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2009-11-13-VirtRegRewriterBug.ll
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2009-11-16-MachineLICM.ll
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2009-11-16-UnfoldMemOpBug.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2009-11-17-UpdateTerminator.ll
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2009-11-18-TwoAddrKill.ll
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2009-11-25-ImpDefBug.ll
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2009-12-01-EarlyClobberBug.ll
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2009-12-11-TLSNoRedZone.ll
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2010-01-05-ZExt-Shl.ll
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2010-01-07-ISelBug.ll
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2010-01-08-Atomic64Bug.ll
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2010-01-11-ExtraPHIArg.ll
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2010-01-13-OptExtBug.ll
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2010-01-15-SelectionDAGCycle.ll
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2010-01-18-DbgValue.ll
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2010-01-19-OptExtBug.ll
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2010-02-01-DbgValueCrash.ll
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2010-02-01-TaillCallCrash.ll
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2010-02-03-DualUndef.ll
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2010-02-04-SchedulerBug.ll
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2010-02-11-NonTemporal.ll
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2010-02-12-CoalescerBug-Impdef.ll
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2010-02-15-ImplicitDefBug.ll
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2010-02-19-TailCallRetAddrBug.ll
Reapply ARM: Do not spill CSR to stack on entry to noreturn functions
2018-04-07 10:57:03 +00:00
2010-02-23-DAGCombineBug.ll
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2010-02-23-DIV8rDefinesAX.ll
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2010-02-23-RematImplicitSubreg.ll
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2010-02-23-SingleDefPhiJoin.ll
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2010-03-04-Mul8Bug.ll
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2010-03-05-ConstantFoldCFG.ll
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2010-03-05-EFLAGS-Redef.ll
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2010-03-17-ISelBug.ll
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2010-04-06-SSEDomainFixCrash.ll
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2010-04-08-CoalescerBug.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2010-04-13-AnalyzeBranchCrash.ll
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2010-04-21-CoalescerBug.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2010-04-29-CoalescerCrash.ll
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2010-04-30-LocalAlloc-LandingPad.ll
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2010-05-03-CoalescerSubRegClobber.ll
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2010-05-05-LocalAllocEarlyClobber.ll
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2010-05-06-LocalInlineAsmClobber.ll
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2010-05-07-ldconvert.ll
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2010-05-10-DAGCombinerBug.ll
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2010-05-12-FastAllocKills.ll
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
2018-02-09 00:10:31 +00:00
2010-05-16-nosseconversion.ll
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2010-05-25-DotDebugLoc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2010-05-26-DotDebugLoc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2010-05-26-FP_TO_INT-crash.ll
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2010-05-28-Crash.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2010-06-01-DeadArg-DbgInfo.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
2010-06-09-FastAllocRegisters.ll
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2010-06-14-fast-isel-fs-load.ll
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2010-06-15-FastAllocEarlyCLobber.ll
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2010-06-24-g-constraint-crash.ll
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2010-06-25-asm-RA-crash.ll
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2010-06-25-CoalescerSubRegDefDead.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2010-06-28-FastAllocTiedOperand.ll
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2010-06-28-matched-g-constraint.ll
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2010-07-02-asm-alignstack.ll
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2010-07-02-UnfoldBug.ll
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2010-07-06-asm-RIP.ll
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2010-07-06-DbgCrash.ll
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2010-07-11-FPStackLoneUse.ll
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2010-07-13-indirectXconstraint.ll
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2010-07-15-Crash.ll
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2010-07-29-SetccSimplify.ll
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2010-08-04-MaskedSignedCompare.ll
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2010-08-04-MingWCrash.ll
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2010-08-04-StackVariable.ll
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2010-09-01-RemoveCopyByCommutingDef.ll
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2010-09-16-asmcrash.ll
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2010-09-16-EmptyFilename.ll
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2010-09-17-SideEffectsInChain.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2010-09-30-CMOV-JumpTable-PHI.ll
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2010-10-08-cmpxchg8b.ll
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2010-11-02-DbgParameter.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2010-11-09-MOVLPS.ll
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2010-11-18-SelectOfExtload.ll
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2011-01-07-LegalizeTypesCrash.ll
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2011-01-10-DagCombineHang.ll
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2011-01-24-DbgValue-Before-Use.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2011-02-04-FastRegallocNoFP.ll
…
2011-02-12-shuffle.ll
…
2011-02-21-VirtRegRewriter-KillSubReg.ll
…
2011-02-23-UnfoldBug.ll
…
2011-02-27-Fpextend.ll
…
2011-03-02-DAGCombiner.ll
…
2011-03-08-Sched-crash.ll
…
2011-03-09-Physreg-Coalescing.ll
…
2011-03-30-CreateFixedObjCrash.ll
…
2011-04-13-SchedCmpJmp.ll
…
2011-04-19-sclr-bb.ll
…
2011-05-09-loaduse.ll
…
2011-05-26-UnreachableBlockElim.ll
…
2011-05-27-CrossClassCoalescing.ll
…
2011-06-01-fildll.ll
…
2011-06-03-x87chain.ll
…
2011-06-06-fgetsign80bit.ll
…
2011-06-12-FastAllocSpill.ll
…
2011-06-14-mmx-inlineasm.ll
…
2011-06-14-PreschedRegalias.ll
…
2011-06-19-QuicksortCoalescerBug.ll
…
2011-07-13-BadFrameIndexDisplacement.ll
…
2011-08-23-PerformSubCombine128.ll
…
2011-08-23-Trampoline.ll
…
2011-08-29-BlockConstant.ll
…
2011-08-29-InitOrder.ll
…
2011-09-14-valcoalesce.ll
…
2011-09-18-sse2cmp.ll
…
2011-09-21-setcc-bug.ll
…
2011-10-11-SpillDead.ll
…
2011-10-11-srl.ll
…
2011-10-12-MachineCSE.ll
…
2011-10-18-FastISel-VectorParams.ll
…
2011-10-19-LegelizeLoad.ll
…
2011-10-19-widen_vselect.ll
[DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros
2018-06-27 18:16:40 +00:00
2011-10-21-widen-cmp.ll
…
2011-10-27-tstore.ll
…
2011-10-30-padd.ll
…
2011-11-07-LegalizeBuildVector.ll
…
2011-11-22-AVX2-Domains.ll
…
2011-11-30-or.ll
…
2011-12-8-bitcastintprom.ll
[X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding (Reapplied)
2018-01-22 12:05:17 +00:00
2011-12-06-AVXVectorExtractCombine.ll
…
2011-12-06-BitcastVectorGlobal.ll
…
2011-12-08-AVXISelBugs.ll
…
2011-12-15-vec_shift.ll
…
2011-12-26-extractelement-duplicate-load.ll
…
2011-12-28-vselecti8.ll
…
2011-20-21-zext-ui2fp.ll
…
2012-1-10-buildvector.ll
…
2012-01-10-UndefExceptionEdge.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2012-01-11-split-cv.ll
…
2012-01-12-extract-sv.ll
[X86] Use 128-bit ops for 256-bit vzmovl patterns.
2018-07-15 18:51:07 +00:00
2012-01-16-mfence-nosse-flags.ll
…
2012-01-18-vbitcast.ll
[X86] Remove duplicate CHECK-LABEL line the update script didn't delete when I converted the test.
2018-02-13 01:36:27 +00:00
2012-02-12-dagco.ll
…
2012-02-14-scalar.ll
…
2012-02-23-mmx-inlineasm.ll
…
2012-02-29-CoalescerBug.ll
…
2012-03-15-build_vector_wl.ll
…
2012-03-20-LargeConstantExpr.ll
…
2012-03-26-PostRALICMBug.ll
…
2012-04-09-TwoAddrPassBug.ll
…
2012-04-26-sdglue.ll
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC
2018-06-04 22:09:26 +00:00
2012-05-17-TwoAddressBug.ll
…
2012-05-19-CoalescerCrash.ll
…
2012-07-10-extload64.ll
…
2012-07-10-shufnorm.ll
…
2012-07-15-broadcastfold.ll
…
2012-07-15-BuildVectorPromote.ll
…
2012-07-15-tconst_shl.ll
…
2012-07-15-vshl.ll
…
2012-07-16-fp2ui-i1.ll
…
2012-07-16-LeaUndef.ll
…
2012-07-17-vtrunc.ll
…
2012-07-23-select_cc.ll
…
2012-08-07-CmpISelBug.ll
…
2012-08-16-setcc.ll
[X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just before isel to enable test instruction matching
2018-02-01 17:08:39 +00:00
2012-08-17-legalizer-crash.ll
…
2012-08-28-UnsafeMathCrash.ll
…
2012-09-13-dagco-fneg.ll
…
2012-09-28-CGPBug.ll
…
2012-10-02-DAGCycle.ll
…
2012-10-03-DAGCycle.ll
…
2012-10-18-crash-dagco.ll
…
2012-11-28-merge-store-alias.ll
…
2012-12-1-merge-multiple.ll
…
2012-12-12-DAGCombineCrash.ll
…
2012-12-14-v8fp80-crash.ll
…
2012-12-19-NoImplicitFloat.ll
…
2013-01-09-DAGCombineBug.ll
…
2013-03-13-VEX-DestReg.ll
…
2013-05-06-ConactVectorCrash.ll
…
2013-10-14-FastISel-incorrect-vreg.ll
…
2014-05-29-factorial.ll
…
2014-08-29-CompactUnwind.ll
…
9601.ll
…
20090313-signext.ll
…
abi-isel.ll
…
absolute-bit-mask.ll
…
absolute-bt.ll
…
absolute-cmp.ll
…
absolute-constant.ll
…
absolute-rotate.ll
…
add32ri8.ll
…
add_shl_constant.ll
…
add-ext.ll
…
add-i64.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
add-of-carry.ll
…
add-sub-nsw-nuw.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
add.ll
[DAGcombine] Teach the combiner about -a = ~a + 1
2018-06-04 19:23:22 +00:00
addcarry2.ll
[X86] Extend load-op-store fusion merge to ADC/SBB.
2018-01-19 15:37:57 +00:00
addcarry.ll
[DAGcombine] Teach the combiner about -a = ~a + 1
2018-06-04 19:23:22 +00:00
addr-label-difference.ll
…
addr-mode-matcher.ll
…
addr-of-ret-addr.ll
…
address-type-promotion-constantexpr.ll
…
addrsig.ll
CodeGen: Don't create address significance table entries for thread-local variables.
2018-07-18 00:21:40 +00:00
adx-intrinsics.ll
…
adx-schedule.ll
[X86] Split WriteADC/WriteADCRMW scheduler classes
2018-05-17 12:43:42 +00:00
aes_intrinsics.ll
…
aes-schedule.ll
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets
2018-03-24 15:05:12 +00:00
alias-gep.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
alias-static-alloca.ll
…
aliases.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
aligned-comm.ll
…
aligned-variadic.ll
…
alignment-2.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
alignment.ll
…
all-ones-vector.ll
…
alldiv-divdi3.ll
…
alloca-align-rounding-32.ll
…
alloca-align-rounding.ll
…
allrem-moddi3.ll
…
and-encoding.ll
[X86] Teach X86DAGToDAGISel::shrinkAndImmediate to preserve upper 32 zeroes of a 64 bit mask.
2018-02-05 16:54:07 +00:00
and-load-fold.ll
…
and-or-fold.ll
…
and-sink.ll
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
2018-02-23 11:50:42 +00:00
and-su.ll
Regenerate test results for and-su.ll . NFC
2018-01-27 16:00:10 +00:00
andimm8.ll
[X86] Regenerate and + immediate mask tests
2018-04-08 12:31:52 +00:00
anyext.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
anyregcc-crash.ll
…
anyregcc.ll
…
apm.ll
[X86][SSE3] Regenerate mwait/monitor intrinsic tests
2018-04-08 12:29:11 +00:00
AppendingLinkage.ll
…
arg-cast.ll
…
arg-copy-elide.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
asm-block-labels.ll
…
asm-global-imm.ll
…
asm-indirect-mem.ll
…
asm-invalid-register-class-crasher.ll
…
asm-label2.ll
…
asm-label.ll
…
asm-mismatched-types.ll
…
asm-modifier-P.ll
…
asm-modifier.ll
…
asm-reg-type-mismatch.ll
…
asm-reject-reg-type-mismatch.ll
…
asm-reject-rex.ll
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode
2018-03-06 18:56:33 +00:00
asm-reject-xmm16.ll
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode
2018-03-06 18:56:33 +00:00
atom-call-reg-indirect-foldedreload32.ll
…
atom-call-reg-indirect-foldedreload64.ll
…
atom-call-reg-indirect.ll
…
atom-cmpb.ll
…
atom-fixup-lea1.ll
…
atom-fixup-lea2.ll
…
atom-fixup-lea3.ll
…
atom-fixup-lea4.ll
…
atom-lea-addw-bug.ll
…
atom-lea-sp.ll
…
atom-pad-short-functions.ll
…
atom-sched.ll
…
atom-shuf.ll
[X86] Regenerate atom pshufb test
2018-04-07 19:50:09 +00:00
atomic8.ll
…
atomic16.ll
…
atomic32.ll
[X86] Regenerate atomic i32 tests
2018-02-07 13:28:23 +00:00
atomic64.ll
…
atomic128.ll
…
atomic6432.ll
…
atomic_add.ll
…
atomic_idempotent.ll
…
atomic_mi.ll
…
atomic_op.ll
…
atomic-dagsched.ll
…
atomic-eflags-reuse.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
atomic-flags.ll
…
atomic-load-store-wide.ll
…
atomic-load-store.ll
…
atomic-minmax-i6432.ll
…
atomic-non-integer.ll
…
atomic-ops-ancient-64.ll
…
atomic-or.ll
…
atomic-pointer.ll
…
Atomics-64.ll
…
attribute-sections.ll
…
avg-mask.ll
[X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the default of promoting to v32i8.
2018-01-23 14:25:39 +00:00
avg.ll
[X86][SSE] Consistently prefer lowering to PACKUS over PACKSS
2018-06-08 10:29:00 +00:00
avoid_complex_am.ll
…
avoid-lea-scale2.ll
…
avoid-loop-align-2.ll
…
avoid-loop-align.ll
…
avoid-sfb-kill-flags.mir
[X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
2018-04-26 13:16:11 +00:00
avoid-sfb-offset.mir
[X86] - Avoid SFB pass - fix bug in updating the offsets for newly created copies
2018-05-21 16:23:16 +00:00
avoid-sfb-overlaps.ll
[X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
2018-04-26 13:16:11 +00:00
avoid-sfb.ll
[X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
2018-04-26 13:16:11 +00:00
avx1-logical-load-folding.ll
…
avx2-arith.ll
…
avx2-cmp.ll
…
avx2-conversions.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx2-fma-fneg-combine.ll
[x86]Add a test case to show missed vfnmadd generation.
2018-07-06 00:31:33 +00:00
avx2-gather.ll
…
avx2-intrinsics-fast-isel.ll
[Utils][X86] Help update_llc_test_checks.py to recognise retl/retq to reduce CHECK duplication (PR35003)
2018-06-01 13:37:01 +00:00
avx2-intrinsics-x86-upgrade.ll
[x86] Revert r330322 (& r330323): Lowering x86 adds/addus/subs/subus intrinsics
2018-04-26 21:46:01 +00:00
avx2-intrinsics-x86.ll
[x86] Revert r330322 (& r330323): Lowering x86 adds/addus/subs/subus intrinsics
2018-04-26 21:46:01 +00:00
avx2-logic.ll
…
avx2-masked-gather.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx2-nontemporal.ll
…
avx2-phaddsub.ll
…
avx2-pmovxrm.ll
…
avx2-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
avx2-shift.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx2-vbroadcast.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
avx2-vbroadcasti128.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
avx2-vector-shifts.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx2-vperm.ll
…
avx512-adc-sbb.ll
…
avx512-any_extend_load.ll
[X86] Remove -mcpu=skx/knl from some tests and use -mattr instead.
2018-04-17 17:30:06 +00:00
avx512-arith.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-bugfix-23634.ll
…
avx512-bugfix-25270.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
avx512-bugfix-26264.ll
…
avx512-build-vector.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-calling-conv.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
avx512-cmp-kor-sequence.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
avx512-cmp.ll
[X86] Don't use EXTRACT_ELEMENT from v1i1 with i8/i32 result type when we need to guarantee zeroes in the upper bits of return.
2018-02-28 08:14:28 +00:00
avx512-cvt.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
avx512-cvttp2i.ll
[x86] fix mappings of cvttp2si/cvttp2ui x86 intrinsics to x86-specific nodes and isel patterns (PR37551)
2018-06-14 03:16:58 +00:00
avx512-ext.ll
[X86] Remove -mcpu=skx/knl from some tests and use -mattr instead.
2018-04-17 17:30:06 +00:00
avx512-extract-subvector-load-store.ll
X86 Tests: Update more isel tests with FastVariableShuffle feature
2018-01-09 16:26:06 +00:00
avx512-extract-subvector.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-fma-commute.ll
…
avx512-fma-intrinsics-upgrade.ll
[X86] Cleanup some of the avx512 masked fma tests to prepare for removing and autoupgrading.
2018-07-06 03:42:06 +00:00
avx512-fma-intrinsics.ll
[X86] In combineFMA, make sure we bitcast the result of isFNEG back the expected type before creating the new FMA node.
2018-07-09 17:43:24 +00:00
avx512-fma.ll
…
avx512-fsel.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
avx512-gather-scatter-intrin.ll
…
avx512-gfni-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512-hadd-hsub.ll
[DAGCombiner] Add EXTRACT_SUBVECTOR to SimplifyDemandedVectorElts
2018-07-07 17:30:06 +00:00
avx512-i1test.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
avx512-inc-dec.ll
…
avx512-insert-extract_i1.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-insert-extract.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
avx512-intel-ocl.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
avx512-intrinsics-canonical.ll
[X86] Add support for combining FMSUB/FNMADD/FNMSUB ISD nodes with an fneg input.
2018-07-05 02:52:56 +00:00
avx512-intrinsics-fast-isel.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
avx512-intrinsics-upgrade.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
avx512-intrinsics.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
avx512-load-store.ll
[X86] Add new patterns for masked scalar load/store to match clang's codegen from r331958.
2018-05-10 21:49:16 +00:00
avx512-load-trunc-store-i1.ll
[X86] Combine (store (v1i1 (scalar_to_vector (i8 X)))) -> (store (i8 X)).
2018-03-04 01:48:02 +00:00
avx512-logic.ll
…
avx512-mask-op.ll
[X86] Use setcc ISD opcode for AVX512 integer comparisons all the way to isel
2018-06-20 21:05:02 +00:00
avx512-mask-spills.ll
…
avx512-mask-zext-bugfix.ll
[FastISel] Disable local value sinking by default
2018-04-11 16:03:07 +00:00
avx512-masked_memop-16-8.ll
…
avx512-masked-memop-64-32.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
avx512-memfold.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-mov.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
avx512-nontemporal.ll
…
avx512-pmovxrm.ll
…
avx512-regcall-Mask.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
avx512-regcall-NoMask.ll
[X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on 32-bit targets
2018-05-16 17:40:07 +00:00
avx512-rndscale.ll
[X86] Add full set of patterns for turning ceil/floor/trunc/rint/nearbyint into rndscale with loads, broadcast, and masking.
2018-07-17 05:48:48 +00:00
avx512-rotate.ll
[X86] Remove masking from avx512 rotate intrinsics. Use select in IR instead.
2018-06-30 01:32:04 +00:00
avx512-scalar_mask.ll
[X86] Remove and autoupgrade the scalar fma intrinsics with masking.
2018-07-12 00:29:56 +00:00
avx512-scalar.ll
[X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass.
2018-02-13 04:19:26 +00:00
avx512-scalarIntrinsics.ll
…
avx512-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
avx512-select.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
avx512-shift.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-shuffle-schedule.ll
[X86][SNB] Fix differences between vex/non-vex XMM vector moves (PR37286)
2018-05-25 12:18:11 +00:00
avx512-skx-insert-subvec.ll
[X86] Use vpmovq2m/vpmovd2m for truncate to vXi1 when possible.
2018-02-19 22:07:31 +00:00
avx512-trunc.ll
[X86] Improve unsigned saturation downconvert detection.
2018-05-15 10:24:12 +00:00
avx512-unsafe-fp-math.ll
…
avx512-vbroadcast.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
avx512-vbroadcasti128.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
avx512-vbroadcasti256.ll
…
avx512-vec3-crash.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-vec-cmp.ll
[X86] Stop swapping the operands of AVX512 setge.
2018-02-19 19:23:35 +00:00
avx512-vpclmulqdq.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512-vpermv3-commute.ll
…
avx512-vpternlog-commute.ll
[X86] Remove masking from vpternlog intrinsics. Use a select in IR instead.
2018-05-21 20:58:09 +00:00
avx512-vselect-crash.ll
…
avx512-vselect.ll
[X86] Use vpmovq2m/vpmovd2m for truncate to vXi1 when possible.
2018-02-19 22:07:31 +00:00
avx512bw-arith.ll
[X86][AVX512BW] Regenerate arithmetic tests using update_llc_test_checks.py script
2018-06-03 14:31:30 +00:00
avx512bw-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512bw-intrinsics-upgrade.ll
[X86] Remove masking from dbpsadbw intrinsics, use select in IR instead.
2018-06-11 06:18:22 +00:00
avx512bw-intrinsics.ll
[X86] Remove masking from dbpsadbw intrinsics, use select in IR instead.
2018-06-11 06:18:22 +00:00
avx512bw-mask-op.ll
[X86] Add DAG combine to constant fold a bitcast of a vXi1 constant build_vector into a scalar integer.
2018-02-08 22:26:36 +00:00
avx512bw-mov.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512bw-vec-cmp.ll
[X86] Stop swapping the operands of AVX512 setge.
2018-02-19 19:23:35 +00:00
avx512bw-vec-test-testn.ll
[X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations.
2018-02-04 01:43:48 +00:00
avx512bwvl-arith.ll
[X86][AVX512BW] Regenerate arithmetic tests using update_llc_test_checks.py script
2018-06-03 14:31:30 +00:00
avx512bwvl-intrinsics-fast-isel.ll
[X86] Fast-isel tests for lowered truncation intrinsics
2018-07-10 08:26:54 +00:00
avx512bwvl-intrinsics-upgrade.ll
[X86] Remove masking from dbpsadbw intrinsics, use select in IR instead.
2018-06-11 06:18:22 +00:00
avx512bwvl-intrinsics.ll
[X86] Remove masking from dbpsadbw intrinsics, use select in IR instead.
2018-06-11 06:18:22 +00:00
avx512bwvl-mov.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
avx512bwvl-vec-cmp.ll
[X86] Stop swapping the operands of AVX512 setge.
2018-02-19 19:23:35 +00:00
avx512bwvl-vec-test-testn.ll
[X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations.
2018-02-04 01:43:48 +00:00
avx512cd-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512cd-intrinsics-upgrade.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512cd-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512cdvl-intrinsics-upgrade.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512cdvl-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512dq-intrinsics-fast-isel.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
avx512dq-intrinsics-upgrade.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
avx512dq-intrinsics.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
avx512dq-mask-op.ll
[X86] Add DAG combine to constant fold a bitcast of a vXi1 constant build_vector into a scalar integer.
2018-02-08 22:26:36 +00:00
avx512dqvl-intrinsics-fast-isel.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
avx512dqvl-intrinsics-upgrade.ll
[X86] Redefine avx512 packed fpclass intrinsics to return a vXi1 mask and implement the mask input argument using an 'and' IR instruction.
2018-06-26 01:37:02 +00:00
avx512dqvl-intrinsics.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
avx512er-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512f-vec-test-testn.ll
[X86] Reduce the number of isel pattern variations needed for VPTESTM/VPTESTNM matching.
2018-02-19 19:23:31 +00:00
avx512ifma-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512ifma-intrinsics-upgrade.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512ifma-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512ifmavl-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512ifmavl-intrinsics-upgrade.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512ifmavl-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vbmi2-intrinsics-fast-isel.ll
[X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
2018-06-13 07:19:21 +00:00
avx512vbmi2-intrinsics-upgrade.ll
[X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
2018-06-13 07:19:21 +00:00
avx512vbmi2-intrinsics.ll
[X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
2018-06-13 07:19:21 +00:00
avx512vbmi2vl-intrinsics-fast-isel.ll
[X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
2018-06-13 07:19:21 +00:00
avx512vbmi2vl-intrinsics-upgrade.ll
[X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
2018-06-13 07:19:21 +00:00
avx512vbmi2vl-intrinsics.ll
[X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
2018-06-13 07:19:21 +00:00
avx512vbmi-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vbmi-intrinsics-upgrade.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vbmi-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vbmivl-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vbmivl-intrinsics-upgrade.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vbmivl-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vl_vnni-intrinsics-upgrade.ll
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
2018-06-03 23:24:17 +00:00
avx512vl_vnni-intrinsics.ll
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
2018-06-03 23:24:17 +00:00
avx512vl-arith.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
avx512vl-intrinsics-canonical.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vl-intrinsics-fast-isel.ll
[X86] Fast-isel tests for lowered truncation intrinsics
2018-07-10 08:26:54 +00:00
avx512vl-intrinsics-upgrade.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
avx512vl-intrinsics.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
avx512vl-logic.ll
…
avx512vl-mov.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
avx512vl-nontemporal.ll
…
avx512vl-vbroadcast.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
avx512vl-vec-cmp.ll
[X86] Stop swapping the operands of AVX512 setge.
2018-02-19 19:23:35 +00:00
avx512vl-vec-masked-cmp.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
avx512vl-vec-test-testn.ll
[X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations.
2018-02-04 01:43:48 +00:00
avx512vl-vpclmulqdq.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vlcd-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vnni-intrinsics-upgrade.ll
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
2018-06-03 23:24:17 +00:00
avx512vnni-intrinsics.ll
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
2018-06-03 23:24:17 +00:00
avx512vpopcntdq-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vpopcntdq-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
avx-arith.ll
…
avx-basic.ll
…
avx-bitcast.ll
…
avx-brcond.ll
Regenrate test results for avx-brcond.ll . NFC
2018-01-27 16:44:00 +00:00
avx-cast.ll
[X86][SSE] Utilize ZeroableElements for canWidenShuffleElements
2018-07-12 13:29:41 +00:00
avx-cmp.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
avx-cvt-2.ll
…
avx-cvt-3.ll
…
avx-cvt.ll
[X86] Add isel patterns for folding loads when creating ROUND instructions from ffloor/fnearbyint/fceil/frint/ftrunc.
2018-06-12 00:48:57 +00:00
avx-cvttp2si.ll
[DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros
2018-06-27 18:16:40 +00:00
avx-fp2int.ll
…
avx-gfni-intrinsics.ll
…
avx-insertelt.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx-intel-ocl.ll
…
avx-intrinsics-fast-isel.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
avx-intrinsics-x86_64.ll
[X86][SSE] Cleanup AVX1 intrinsics tests
2018-06-02 21:35:48 +00:00
avx-intrinsics-x86-upgrade.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
avx-intrinsics-x86.ll
[X86] Lowering sqrt intrinsics to native IR
2018-06-15 18:05:24 +00:00
avx-isa-check.ll
…
avx-load-store.ll
[X86] Use 128-bit ops for 256-bit vzmovl patterns.
2018-07-15 18:51:07 +00:00
avx-logic.ll
[x86] be more selective about converting 'and' to shuffle (PR37749)
2018-06-14 19:55:02 +00:00
avx-minmax.ll
…
avx-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
avx-select.ll
…
avx-shift.ll
…
avx-shuffle-x86_32.ll
…
avx-splat.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
avx-trunc.ll
…
avx-unpack.ll
…
avx-varargs-x86_64.ll
…
avx-vbroadcast.ll
…
avx-vbroadcastf128.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
avx-vextractf128.ll
…
avx-vinsertf128.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx-vpclmulqdq.ll
…
avx-vperm2x128.ll
[DAGCombiner] Add EXTRACT_SUBVECTOR to SimplifyDemandedVectorElts
2018-07-07 17:30:06 +00:00
avx-vzeroupper.ll
[X86] Re-generate test to get proper capitalization of its CHECK lines. NFC
2018-03-13 23:31:48 +00:00
avx-win64-args.ll
…
avx-win64.ll
…
avx.ll
…
backpropmask.ll
[x86] restore test comment; NFC
2018-06-08 13:53:13 +00:00
bad-tls-fold.mir
[x86] Fix nasty bug in the x86 backend that is essentially impossible to
2018-02-07 23:59:14 +00:00
barrier-sse.ll
…
barrier.ll
…
base-pointer-and-cmpxchg.ll
…
basic-promote-integers.ll
…
bc-extract.ll
…
bigstructret2.ll
…
bigstructret.ll
…
bit-piece-comment.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
bit-test-shift.ll
…
bitcast2.ll
…
bitcast-and-setcc-128.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bitcast-and-setcc-256.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bitcast-and-setcc-512.ll
[SelectionDAG][ARM][X86] Teach PromoteIntRes_SETCC to do a better job picking the result type for the setcc.
2018-03-15 23:04:11 +00:00
bitcast-i256.ll
…
bitcast-int-to-vector-bool-sext.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bitcast-int-to-vector-bool-zext.ll
[X86] Legalize zero extends from vXi1 to vXi16/vXi32/vXi64 using a sign extend and a shift.
2018-02-10 08:06:52 +00:00
bitcast-int-to-vector-bool.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bitcast-int-to-vector.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bitcast-mmx.ll
[X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead.
2018-01-05 20:55:12 +00:00
bitcast-setcc-128.ll
[X86] Post process the DAG after isel to remove vector moves that were added to zero upper bits.
2018-03-16 17:13:42 +00:00
bitcast-setcc-256.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bitcast-setcc-512.ll
[X86] Add a custom legalization for (i16 (bitcast v16i1)) and (i32 (bitcast v32i1)) without AVX512 to prevent scalarization
2018-02-26 20:32:27 +00:00
bitcast.ll
…
bitcnt-false-dep.ll
[X86] Enable popcnt false dependency breaking on Silvermont and Goldmont.
2018-04-19 19:25:24 +00:00
bitreverse.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
block-placement.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
block-placement.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bmi2-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
bmi2-x86_64.ll
[X86][BMI2] Test i32 intrinsics on 32/64 bits + branch off i64 tests
2018-06-02 17:22:13 +00:00
bmi2.ll
[X86][BMI2] Test i32 intrinsics on 32/64 bits + branch off i64 tests
2018-06-02 17:22:13 +00:00
bmi-intrinsics-fast-isel-x86_64.ll
…
bmi-intrinsics-fast-isel.ll
[FastISel] Disable local value sinking by default
2018-04-11 16:03:07 +00:00
bmi-schedule.ll
[X86][BMI1] Remove test for non-existent andn i16 instruction
2018-06-02 17:02:27 +00:00
bmi-x86_64.ll
[X86][BMI][TBM] Only demand bottom 16-bits of the BEXTR control op (PR34042)
2018-06-06 10:52:10 +00:00
bmi.ll
[NFC][X86][AArch64] Reorganize/cleanup BZHI test patterns
2018-06-06 19:38:10 +00:00
bool-ext-inc.ll
…
bool-math.ll
[X86] Use XOR for SUB (C, X) during isel if will help fold an immediate
2018-06-26 03:11:15 +00:00
bool-simplify.ll
[X86] Promote 16-bit cmovs to 32-bits
2018-02-20 17:41:00 +00:00
bool-vector.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
bool-zext.ll
…
br-fold.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
branch_instruction_and_target_split_perf_nops.mir
…
branchfolding-catchpads.ll
…
branchfolding-debugloc.ll
[CodeGen] Add a new pass for PostRA sink
2018-03-22 20:06:47 +00:00
branchfolding-landingpads.ll
…
branchfolding-undef.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
brcond.ll
Regenrate brcond.ll test results. NFC
2018-01-27 16:57:15 +00:00
break-anti-dependencies.ll
…
break-false-dep.ll
[X86] Add avx512vl command line to break-false-dep.ll
2018-07-03 04:43:49 +00:00
broadcast-elm-cross-splat-vec.ll
[DAGCombiner] Allow visitEXTRACT_SUBVECTOR to combine with BUILD_VECTORS between LegalizeVectorOps and LegalizeDAG.
2018-03-13 20:36:28 +00:00
broadcastm-lowering.ll
[X86] Use setcc ISD opcode for AVX512 integer comparisons all the way to isel
2018-06-20 21:05:02 +00:00
bss_pagealigned.ll
…
bswap_tree2.ll
…
bswap_tree.ll
…
bswap-inline-asm.ll
…
bswap-rotate.ll
…
bswap-vector.ll
…
bswap-wide-int.ll
…
bswap.ll
[X86] Autogenerate complete checks on a couple tests. NFC
2018-01-19 22:04:20 +00:00
bt.ll
…
btc_bts_btr.ll
[X86] Suppress load folding into and/or/xor if it will prevent matching btr/bts/btc.
2018-06-28 17:58:01 +00:00
btq.ll
…
bug26810.ll
Take into account the cost of local intervals when selecting split candidate.
2018-01-31 13:31:08 +00:00
bug37521.ll
DAG: Fix crash on shift with large shift amounts
2018-05-18 21:54:16 +00:00
build-vector-128.ll
…
build-vector-256.ll
…
build-vector-512.ll
[X86] Remove some composite MOVSS/MOVSD isel patterns.
2018-07-11 04:51:40 +00:00
buildvec-insertvec.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
bypass-slow-division-32.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bypass-slow-division-64.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bypass-slow-division-tune.ll
…
byval2.ll
…
byval3.ll
…
byval4.ll
…
byval5.ll
…
byval6.ll
…
byval7.ll
…
byval-align.ll
…
byval-callee-cleanup.ll
…
byval.ll
…
cache-intrinsic.ll
…
call-imm.ll
…
call-push.ll
…
cas.ll
…
cast-vsel.ll
…
catch.ll
Align stubs for external and common global variables to pointer size.
2018-04-02 23:20:30 +00:00
catchpad-dynamic-alloca.ll
…
catchpad-lifetime.ll
…
catchpad-realign-savexmm.ll
…
catchpad-regmask.ll
…
catchpad-reuse.ll
…
catchpad-weight.ll
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
2018-02-09 00:10:31 +00:00
catchret-empty-fallthrough.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
catchret-fallthrough.ll
…
catchret-regmask.ll
…
cfi-inserter-cfg-with-merge.mir
Use iteration instead of recursion in CFIInserter
2018-05-11 15:54:46 +00:00
cfi-inserter-check-order.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
cfi-inserter-verify-inconsistent-offset.mir
Add option -verify-cfiinstrs to run verifier in CFIInstrInserter
2018-05-07 14:09:33 +00:00
cfi-inserter-verify-inconsistent-register.mir
Add option -verify-cfiinstrs to run verifier in CFIInstrInserter
2018-05-07 14:09:33 +00:00
cfi-xmm.ll
…
cfi.ll
…
cfstring.ll
…
chain_order.ll
…
change-compare-stride-1.ll
…
change-compare-stride-trickiness-0.ll
…
change-compare-stride-trickiness-1.ll
…
change-compare-stride-trickiness-2.ll
…
change-unsafe-fp-math.ll
…
cldemote-intrinsic.ll
[X86] Introduce cldemote instruction
2018-04-13 07:35:08 +00:00
cleanuppad-inalloca.ll
…
cleanuppad-large-codemodel.ll
Revert "Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models""
2018-06-28 17:56:43 +00:00
cleanuppad-realign.ll
…
clear_upper_vector_element_bits.ll
[X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles and the root started as a float domain shuffle
2018-02-16 14:57:25 +00:00
clear-highbits.ll
[X86][TLI] DAGCombine: Unfold variable bit-clearing mask to two shifts.
2018-07-09 19:06:42 +00:00
clear-lowbits.ll
[X86][TLI] DAGCombine: Unfold variable bit-clearing mask to two shifts.
2018-07-09 19:06:42 +00:00
clflushopt-schedule.ll
…
clflushopt.ll
…
clwb-schedule.ll
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
2018-04-06 11:00:51 +00:00
clwb.ll
[X86] Split up -march=icelake to -client & -server
2018-04-10 18:59:13 +00:00
clz.ll
[X86] Add test cases that exercise the BSR/BSF optimization combineCMov.
2018-02-06 21:47:04 +00:00
clzero-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
clzero.ll
…
cmov-double.ll
…
cmov-fp.ll
…
cmov-into-branch.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cmov-promotion.ll
[X86] Allow CMOVs of constants to be sign extended from i32.
2018-02-16 07:16:15 +00:00
cmov-schedule.ll
[X86] Give CMOV 2 cycle latency on SLM.
2018-04-18 06:04:30 +00:00
cmov.ll
[CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions
2018-06-05 21:03:52 +00:00
cmovcmov.ll
…
cmp-fast-isel.ll
…
cmp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
cmpxchg8b_alloca_regalloc_handling.ll
…
cmpxchg8b.ll
[X86] Regenerate cmpxchg tests
2018-02-28 22:57:23 +00:00
cmpxchg16b.ll
[X86] Regenerate cmpxchg tests
2018-02-28 22:57:23 +00:00
cmpxchg-clobber-flags.ll
[x86] Switch EFLAGS copy lowering to use reg-reg form of testing for
2018-04-18 15:52:50 +00:00
cmpxchg-i1.ll
…
cmpxchg-i128-i1.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
coal-sections.ll
…
coalesce_commute_movsd.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
coalesce_commute_subreg.ll
…
coalesce-esp.ll
…
coalesce-implicitdef.ll
…
coalescer-commute1.ll
…
coalescer-commute2.ll
…
coalescer-commute3.ll
…
coalescer-commute4.ll
…
coalescer-commute5.ll
…
coalescer-cross.ll
…
coalescer-dce2.ll
…
coalescer-dce.ll
…
coalescer-identity.ll
…
coalescer-remat.ll
…
coalescer-subreg.ll
…
coalescer-win64.ll
…
code_placement_align_all.ll
…
code_placement_cold_loop_blocks.ll
…
code_placement_eh.ll
…
code_placement_ignore_succ_in_inner_loop.ll
…
code_placement_loop_rotation2.ll
…
code_placement_loop_rotation3.ll
…
code_placement_loop_rotation.ll
…
code_placement.ll
…
codegen-prepare-addrmode-sext.ll
…
codegen-prepare-cast.ll
…
codegen-prepare-crash.ll
…
codegen-prepare-extload.ll
…
codegen-prepare.ll
…
codemodel.ll
…
coff-comdat2.ll
…
coff-comdat3.ll
…
coff-comdat.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
coff-feat00.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
coff-no-dead-strip.ll
[CodeGen] Ignore private symbols in llvm.used for COFF
2018-01-26 00:15:25 +00:00
coff-weak.ll
…
coldcc64.ll
…
combine-64bit-vec-binop.ll
…
combine-abs.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
combine-add.ll
…
combine-and.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
combine-avx2-intrinsics.ll
…
combine-avx-intrinsics.ll
…
combine-fabs.ll
[X86][SSE] Add some basic FABS combine tests
2018-01-10 13:28:34 +00:00
combine-fcopysign.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
combine-lds.ll
…
combine-mul.ll
[X86] Remove sse41 specific code from lowering v16i8 multiply
2018-03-19 17:31:41 +00:00
combine-multiplies.ll
…
combine-or.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
combine-pmuldq.ll
[X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of lowering.
2018-04-07 19:09:52 +00:00
combine-rotates.ll
[X86][SSE] Add SSE2/AVX2 vector rotate tests
2018-06-08 14:07:21 +00:00
combine-sdiv.ll
[X86][XOP] Fix SUB constant folding for VPSHA/VPSHL shift lowering
2018-07-20 16:55:18 +00:00
combine-select.ll
[X86] Fix a potential crash that occur after r333419.
2018-05-29 20:04:10 +00:00
combine-sext-in-reg.ll
…
combine-shl.ll
[X86][SSE] Prefer BLEND(SHL(v,c1),SHL(v,c2)) over MUL(v, c3)
2018-07-10 07:58:33 +00:00
combine-smax.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
combine-smin.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
combine-sra.ll
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)
2018-05-16 20:52:52 +00:00
combine-srem.ll
[DAGCombiner] Fold X - (-Y *Z) -> X + (Y * Z)
2018-07-20 01:40:03 +00:00
combine-srl.ll
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)
2018-05-16 20:52:52 +00:00
combine-sse41-intrinsics.ll
…
combine-sub.ll
…
combine-testm-and.ll
[X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations.
2018-02-04 01:43:48 +00:00
combine-udiv.ll
[X86] Add UDIV by uniform/non-uniform constant tests
2018-07-12 09:04:28 +00:00
combine-umax.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
combine-umin.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
combine-urem.ll
[DAGCombiner] Add (urem X, -1) -> select(X == -1, 0, x) fold
2018-07-11 09:14:37 +00:00
commute-3dnow.ll
…
commute-blend-avx2.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
commute-blend-sse41.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
commute-clmul.ll
…
commute-fcmp.ll
[X86] Add a DAG combine to combine (sext (setcc)) with VLX
2018-01-09 18:14:22 +00:00
commute-intrinsic.ll
…
commute-two-addr.ll
…
commute-vpclmulqdq-avx512.ll
…
commute-vpclmulqdq-avx.ll
…
commute-xop.ll
[X86] Mark XOP vpmac* and vpmadc intrinsics as being commutative so that tablegen will generate patterns with the load in operand 0.
2018-02-20 03:58:14 +00:00
commuted-blend-mask.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
compact-unwind.ll
…
compare_folding.ll
…
compare-add.ll
…
compare-global.ll
…
compare-inf.ll
…
compiler_used.ll
…
complex-asm.ll
…
complex-fastmath.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
complex-fca.ll
…
compress_expand.ll
[X86] Use vpmovq2m/vpmovd2m for truncate to vXi1 when possible.
2018-02-19 22:07:31 +00:00
computeKnownBits_urem.ll
…
conditional-indecrement.ll
…
conditional-tailcall-samedest.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
conditional-tailcall.ll
…
const-base-addr.ll
…
constant-combines.ll
…
constant-hoisting-and.ll
…
constant-hoisting-bfi.ll
…
constant-hoisting-cmp.ll
…
constant-hoisting-optnone.ll
…
constant-hoisting-shift-immediate.ll
…
constant-pool-remat-0.ll
…
constant-pool-sharing.ll
…
constpool.ll
…
constructor.ll
…
convert-2-addr-3-addr-inc64.ll
…
copy-eflags.ll
[x86][eflags] Fix PR37431 by teaching the EFLAGS copy lowering to
2018-05-15 20:16:57 +00:00
copy-propagation.ll
…
copysign-constant-magnitude.ll
…
cpus.ll
[X86] Introduce archs: goldmont-plus & tremont
2018-04-16 07:47:35 +00:00
crash-lre-eliminate-dead-def.ll
…
crash-nosse.ll
…
crash-O0.ll
…
crash.ll
…
critical-anti-dep-breaker.ll
…
critical-edge-split-2.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cse-add-with-overflow.ll
…
cstring.ll
…
ctpop-combine.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cvt16.ll
…
cvtv2f32.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
cxx_tlscc64.ll
…
dag-fmf-cse.ll
…
dag-merge-fast-accesses.ll
…
dag-optnone.ll
…
dag-rauw-cse.ll
…
dag-update-nodetomatch.ll
…
dagcombine-and-setcc.ll
…
dagcombine-buildvector.ll
…
dagcombine-cse.ll
[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT
2018-07-17 09:45:35 +00:00
dagcombine-select.ll
[X86] Try fixing r336768
2018-07-13 20:54:24 +00:00
dagcombine-shifts.ll
…
dagcombine-unsafe-math.ll
[x86] regenerate checks and adjust tests
2018-06-18 20:05:16 +00:00
darwin-bzero.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
darwin-no-dead-strip.ll
…
darwin-preemption.ll
…
darwin-quote.ll
…
darwin-tls.ll
…
dbg-baseptr.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
dbg-changes-codegen-branch-folding2.mir
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
dbg-changes-codegen-branch-folding.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
dbg-changes-codegen.ll
…
dbg-combine.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
dbg-line-0-no-discriminator.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
DbgValueOtherTargets.test
…
debug-nodebug-crash.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debugloc-argsize.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debugloc-no-line-0.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
deopt-bundles.ll
…
deopt-intrinsic-cconv.ll
[Debugify] Don't insert debug values after terminating deopts
2018-06-05 00:56:07 +00:00
deopt-intrinsic.ll
…
disable-tail-calls.ll
…
discontiguous-loops.ll
…
div8.ll
…
div-rem-simplify.ll
…
divide-by-constant.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
divide-windows-itanium.ll
…
divrem8_ext.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
divrem.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
dllexport-x86_64.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
dllexport.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
dllimport-x86_64.ll
…
dllimport.ll
…
dollar-name.ll
…
domain-reassignment-implicit-def.ll
[X86DomainReassignment] Don't delete IMPLICIT_DEF nodes
2018-05-18 00:40:52 +00:00
domain-reassignment-test.ll
[X86DomainReassignment] Hopefully fix buildbot failure
2018-05-18 04:36:38 +00:00
domain-reassignment.mir
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
dont-trunc-store-double-to-float.ll
…
dropped_constructor.ll
…
dwarf-comp-dir.ll
[DebugInfo] Support DWARF v5 source code embedding extension
2018-02-23 23:01:06 +00:00
dwarf-eh-prepare.ll
…
dwarf-headers.ll
[DWARFv5] Put the DWO ID in its place.
2018-05-22 17:27:31 +00:00
dwarf-split-line-1.ll
CodeGen: Add a dwo output file argument to addPassesToEmitFile and hook it up to dwo output.
2018-05-21 20:16:41 +00:00
dwarf-split-line-2.ll
CodeGen: Add a dwo output file argument to addPassesToEmitFile and hook it up to dwo output.
2018-05-21 20:16:41 +00:00
dyn_alloca_aligned.ll
…
dyn-stackalloc.ll
…
dynamic-alloca-in-entry.ll
…
dynamic-alloca-lifetime.ll
…
dynamic-allocas-VLAs.ll
…
dynamic-regmask.ll
[X86] Add phony registers for high halves of regs with low halves
2018-07-02 19:05:09 +00:00
DynamicCalleeSavedRegisters.ll
…
early-cfi-sections.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
early-ifcvt-crash.ll
…
early-ifcvt.ll
…
eh_frame.ll
…
eh-frame-unreachable.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
eh-label.ll
Emit smaller exception tables for non-SJLJ mode.
2018-02-09 17:13:37 +00:00
eh-nolandingpads.ll
…
eh-null-personality.ll
…
eh-unknown.ll
Emit smaller exception tables for non-SJLJ mode.
2018-02-09 17:13:37 +00:00
eip-addressing-i386.ll
[X86][AsmParser] Don't consider %eip as a valid register outside of 32-bit mode.
2018-07-03 17:40:51 +00:00
element-wise-atomic-memory-intrinsics.ll
Changing constants in a test (NFC)
2018-05-08 19:08:12 +00:00
elf-associated.ll
…
elf-comdat2.ll
…
elf-comdat.ll
…
emit-big-cst.ll
…
empty-function.ll
…
empty-functions.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
empty-struct-return-type.ll
…
emutls_generic.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
emutls-pic.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
emutls-pie.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
emutls.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
epilogue-cfi-fp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
epilogue-cfi-no-fp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
epilogue.ll
…
equiv_with_fndef.ll
…
equiv_with_vardef.ll
…
evex-to-vex-compress.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
exception-label.ll
…
exedeps-movq.ll
…
exedepsfix-broadcast.ll
…
expand-opaque-const.ll
…
expand-vr64-gr64-copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
extend-set-cc-uses-dbg.ll
[DAGCombiner] Set the right SDLoc on extended SETCC uses (7/N)
2018-05-11 18:40:10 +00:00
extend.ll
…
extended-fma-contraction.ll
…
extern_weak.ll
…
extmul64.ll
…
extmul128.ll
…
extract-combine.ll
…
extract-concat.ll
…
extract-extract.ll
…
extract-insert.ll
…
extract-lowbits.ll
[X86][TLI] DAGCombine: Unfold variable bit-clearing mask to two shifts.
2018-07-09 19:06:42 +00:00
extract-store.ll
[X86] Don't use aligned load/store instructions for fp128 if the load/store isn't aligned.
2018-07-02 17:01:54 +00:00
extractelement-from-arg.ll
…
extractelement-index.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
extractelement-legalization-cycle.ll
…
extractelement-legalization-store-ordering.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
extractelement-load.ll
[X86] Generate v2f64 X86ISD::UNPCKL/UNPCKH instead of X86ISD::MOVLHPS/MOVHLPS for unary v2f64 {0,0} and {1,1} shuffles with SSE2.
2018-07-18 05:10:51 +00:00
extractelement-shuffle.ll
…
extractps.ll
…
f16c-intrinsics-fast-isel.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
f16c-intrinsics.ll
…
f16c-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
fabs.ll
[SelectionDAG] Removing FABS folding from DAGCombiner
2018-03-30 15:42:52 +00:00
fadd-combines.ll
[DAGCombiner] remove hasOneUse() check from fadd constants transform
2018-06-13 15:22:48 +00:00
fast-cc-callee-pops.ll
…
fast-cc-merge-stack-adj.ll
…
fast-cc-pass-in-regs.ll
…
fast-isel-abort-warm.ll
…
fast-isel-agg-constant.ll
…
fast-isel-args-fail2.ll
…
fast-isel-args-fail.ll
…
fast-isel-args.ll
…
fast-isel-atomic.ll
…
fast-isel-avoid-unnecessary-pic-base.ll
…
fast-isel-bail.ll
…
fast-isel-bc.ll
[X86][MMX] Improve handling of 64-bit MMX constants
2018-03-01 22:22:31 +00:00
fast-isel-bitcasts-avx512.ll
…
fast-isel-bitcasts-avx.ll
…
fast-isel-bitcasts.ll
…
fast-isel-branch_weights.ll
…
fast-isel-call-bool.ll
…
fast-isel-call-cleanup.ll
Revert "Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models""
2018-06-28 17:56:43 +00:00
fast-isel-call.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fast-isel-cmp-branch2.ll
…
fast-isel-cmp-branch3.ll
…
fast-isel-cmp-branch.ll
…
fast-isel-cmp.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fast-isel-constant.ll
…
fast-isel-constpool.ll
Revert "Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models""
2018-06-28 17:56:43 +00:00
fast-isel-constrain-store-indexreg.ll
…
fast-isel-deadcode.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fast-isel-divrem-x86-64.ll
…
fast-isel-divrem.ll
…
fast-isel-double-half-convertion.ll
…
fast-isel-emutls.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
fast-isel-expect.ll
…
fast-isel-extract.ll
…
fast-isel-float-half-convertion.ll
…
fast-isel-fneg.ll
…
fast-isel-fold-mem.ll
…
fast-isel-fptrunc-fpext.ll
[X86] Add more instructions to the memory folding tables using the autogenerated table as a guide.
2018-06-15 05:49:19 +00:00
fast-isel-gc-intrinsics.ll
…
fast-isel-gep.ll
…
fast-isel-gv.ll
…
fast-isel-i1.ll
…
fast-isel-int-float-conversion-x86-64.ll
[X86][FastISel] Add EVEX support to sitofp handling.
2018-07-13 21:03:43 +00:00
fast-isel-int-float-conversion.ll
[X86][FastISel] Add EVEX support to sitofp handling.
2018-07-13 21:03:43 +00:00
fast-isel-load-i1.ll
…
fast-isel-mem.ll
…
fast-isel-movsbl-indexreg.ll
…
fast-isel-nontemporal.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fast-isel-noplt-pic.ll
…
fast-isel-ret-ext.ll
…
fast-isel-select-cmov2.ll
…
fast-isel-select-cmov.ll
…
fast-isel-select-cmp.ll
…
fast-isel-select-pseudo-cmov.ll
…
fast-isel-select-sse.ll
…
fast-isel-select.ll
…
fast-isel-sext-zext.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fast-isel-sext.ll
…
fast-isel-shift.ll
[X86] Add back fast-isel code for handling i8 shifts.
2018-03-14 17:57:19 +00:00
fast-isel-sse12-fptoint.ll
…
fast-isel-stackcheck.ll
…
fast-isel-store.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
fast-isel-tailcall.ll
…
fast-isel-tls.ll
…
fast-isel-trunc-kill-subreg.ll
…
fast-isel-uint-float-conversion-x86-64.ll
[X86][FastISel] Support uitofp with avx512.
2018-07-13 22:09:30 +00:00
fast-isel-uint-float-conversion.ll
[X86][FastISel] Support uitofp with avx512.
2018-07-13 22:09:30 +00:00
fast-isel-vecload.ll
…
fast-isel-x32.ll
…
fast-isel-x86-64.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fast-isel-x86.ll
…
fast-isel.ll
…
fastcall-correct-mangling.ll
…
fastcc3struct.ll
…
fastcc-2.ll
…
fastcc-byval.ll
…
fastcc-sret.ll
…
fastcc.ll
…
fastisel-gep-promote-before-add.ll
…
fastisel-softfloat.ll
…
fastmath-float-half-conversion.ll
…
fcmove.ll
…
fdiv-combine.ll
…
fdiv.ll
…
fentry-insertion.ll
…
field-extract-use-trunc.ll
…
fildll.ll
…
file-directive.ll
…
file-source-filename.ll
…
finite-libcalls.ll
[X86] Properly implement the calling convention for f80 for mingw/x86_64
2018-03-20 06:19:38 +00:00
fixed-stack-di-mir.ll
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
fixup-bw-copy.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
fixup-bw-copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fixup-bw-inst.ll
…
fixup-bw-inst.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fixup-lea.ll
…
flags-copy-lowering.mir
[x86] Fix a capitalization that I failed to save in my editor before
2018-07-13 09:48:04 +00:00
float-asmprint.ll
…
float-conv-elim.ll
…
floor-soft-float.ll
…
fltused_function_pointer.ll
[NFC] fix trivial typos in comments and documents
2018-01-29 05:17:03 +00:00
fltused.ll
[NFC] fix trivial typos in comments and documents
2018-01-29 05:17:03 +00:00
fma4-commute-x86.ll
[X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic instead.
2018-07-06 07:14:41 +00:00
fma4-fneg-combine.ll
[X86] Enhance combineFMA to look for FNEG behind an EXTRACT_VECTOR_ELT.
2018-07-08 18:04:00 +00:00
fma4-intrinsics-x86_64-folded-load.ll
…
fma4-intrinsics-x86-upgrade.ll
[X86] Remove the last of the 'x86.fma.' intrinsics and autoupgrade them to 'llvm.fma'. Add upgrade tests for all.
2018-07-05 18:43:58 +00:00
fma4-intrinsics-x86.ll
[X86] Remove the last of the 'x86.fma.' intrinsics and autoupgrade them to 'llvm.fma'. Add upgrade tests for all.
2018-07-05 18:43:58 +00:00
fma4-scalar-memfold.ll
[X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic instead.
2018-07-06 07:14:41 +00:00
fma4-schedule.ll
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
2018-04-06 11:00:51 +00:00
fma_patterns_wide.ll
…
fma_patterns.ll
…
fma-commute-x86.ll
[X86] Remove X86 specific scalar FMA intrinsics and upgrade to tart independent FMA and extractelement/insertelement.
2018-07-05 06:52:55 +00:00
fma-do-not-commute.ll
…
fma-fneg-combine.ll
[X86] Remove and autoupgrade the scalar fma intrinsics with masking.
2018-07-12 00:29:56 +00:00
fma-intrinsics-canonical.ll
[X86] Lowering FMA intrinsics to native IR (LLVM part)
2018-05-30 15:25:16 +00:00
fma-intrinsics-fast-isel.ll
[X86] Lowering FMA intrinsics to native IR (LLVM part)
2018-05-30 15:25:16 +00:00
fma-intrinsics-phi-213-to-231.ll
…
fma-intrinsics-x86-upgrade.ll
[X86] Remove the last of the 'x86.fma.' intrinsics and autoupgrade them to 'llvm.fma'. Add upgrade tests for all.
2018-07-05 18:43:58 +00:00
fma-intrinsics-x86.ll
[X86] Add a missing FMA3 scalar intrinsic pattern.
2018-07-16 23:10:58 +00:00
fma-phi-213-to-231.ll
…
fma-scalar-combine.ll
[X86] Rename the operands in the recently introduced MOVSS+FMA patterns so that the operand names in the output pattern are always in 1, 2, 3 order since those are the operand names in the instruction.
2018-05-29 20:46:26 +00:00
fma-scalar-memfold.ll
[X86] Remove X86 specific scalar FMA intrinsics and upgrade to tart independent FMA and extractelement/insertelement.
2018-07-05 06:52:55 +00:00
fma-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
fma.ll
[X86] Enable commuting of VUNPCKHPD to VMOVLHPS to enable load folding by using VMOVLPS with a modified address.
2018-07-18 07:31:32 +00:00
fmaddsub-combine.ll
[X86] Add support for matching FMSUBADD from build_vector.
2018-03-15 06:14:55 +00:00
fmaxnum.ll
[DAG] propagate FMF for all FPMathOperators
2018-05-15 14:16:24 +00:00
fmf-flags.ll
Utilize new SDNode flag functionality to expand current support for fadd
2018-06-18 23:44:59 +00:00
fmf-propagation.ll
Fast Math Flag mapping into SDNode
2018-05-04 18:48:20 +00:00
fminnum.ll
[DAG] propagate FMF for all FPMathOperators
2018-05-15 14:16:24 +00:00
fmsubadd-combine.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
fmul-combines.ll
Utilize new SDNode flag functionality to expand current support for fmul
2018-06-12 16:13:11 +00:00
fmul-zero.ll
…
fnabs.ll
…
fold-add.ll
…
fold-and-shift.ll
…
fold-call-2.ll
…
fold-call-3.ll
…
fold-call-oper.ll
…
fold-call.ll
…
fold-imm.ll
…
fold-load-binops.ll
…
fold-load-unops.ll
[X86] Lowering sqrt intrinsics to native IR
2018-06-15 18:05:24 +00:00
fold-load-vec.ll
Regenerate partial vector fold test. NFCI.
2018-07-20 13:58:57 +00:00
fold-load.ll
…
fold-mul-lohi.ll
…
fold-pcmpeqd-1.ll
…
fold-pcmpeqd-2.ll
…
fold-push.ll
…
fold-rmw-ops.ll
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
2018-02-23 11:50:42 +00:00
fold-sext-trunc.ll
[DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N)
2018-05-11 18:40:08 +00:00
fold-tied-op.ll
…
fold-vector-bv-crash.ll
…
fold-vector-sext-crash2.ll
…
fold-vector-sext-crash.ll
[X86] Turn selects with constant condition into vector shuffles during DAG combine
2018-02-17 00:30:30 +00:00
fold-vector-sext-zext.ll
…
fold-vector-shl-crash.ll
…
fold-vector-shuffle-crash.ll
…
fold-vector-trunc-sitofp.ll
…
fold-vex.ll
…
fold-xmm-zero.ll
…
fold-zext-trunc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
fops-windows-itanium.ll
…
force-align-stack-alloca.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
force-align-stack.ll
…
fp2sint.ll
…
fp128-calling-conv.ll
…
fp128-cast.ll
Add support for emitting libcalls for x86_fp80 -> fp128 and vice-versa
2018-01-17 22:29:16 +00:00
fp128-compare.ll
…
fp128-extract.ll
[X86] Regenerate fp128 test
2018-01-14 19:07:41 +00:00
fp128-g.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
fp128-i128.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
fp128-libcalls.ll
…
fp128-load.ll
…
fp128-select.ll
[X86] Don't use aligned load/store instructions for fp128 if the load/store isn't aligned.
2018-07-02 17:01:54 +00:00
fp128-store.ll
…
fp_constant_op.ll
…
fp_load_cast_fold.ll
…
fp_load_fold.ll
…
fp-arith.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
fp-cvt.ll
Go back to sometimes assuming intristics are local.
2018-03-10 02:42:14 +00:00
fp-double-rounding.ll
…
fp-elim-and-no-fp-elim.ll
…
fp-elim.ll
…
fp-fast.ll
…
fp-fold.ll
Utilize new SDNode flag functionality to expand current support for fadd
2018-06-18 23:44:59 +00:00
fp-immediate-shorten.ll
…
fp-in-intregs.ll
…
fp-intrinsics.ll
[FPEnv] Expand constrained FP POWI
2018-06-15 20:57:55 +00:00
fp-load-trunc.ll
…
fp-logic-replace.ll
…
fp-logic.ll
…
fp-select-cmp-and.ll
…
fp-stack-2results.ll
…
fp-stack-compare-cmov.ll
…
fp-stack-compare.ll
…
fp-stack-direct-ret.ll
…
fp-stack-O0-crash.ll
…
fp-stack-O0.ll
…
fp-stack-ret-conv.ll
…
fp-stack-ret-store.ll
…
fp-stack-ret.ll
…
fp-stack-retcopy.ll
…
fp-stack-set-st1.ll
…
fp-stack.ll
…
fp-trunc.ll
…
fp-undef.ll
[DAG] fold FP binops with undef operands to NaN
2018-05-21 23:54:19 +00:00
fp-une-cmp.ll
…
fpcmp-soft-fp.ll
…
fpstack-debuginstr-kill.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
fptosi-constant.ll
[x86] add tests for convert-FP-to-integer with constants; NFC
2018-04-03 18:34:56 +00:00
frame-base.ll
…
frame-lowering-debug-intrinsic-2.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
frame-lowering-debug-intrinsic.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
frame-order.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
frameaddr.ll
…
frameregister.ll
…
frem-msvc32.ll
…
fsgsbase-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
fsgsbase.ll
…
fsxor-alignment.ll
…
ftrunc.ll
[DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros
2018-06-27 18:16:40 +00:00
full-lsr.ll
…
funclet-layout.ll
…
function-alias.ll
…
function-subtarget-features-2.ll
…
function-subtarget-features.ll
…
funnel-shift-rot.ll
[Intrinsics] define funnel shift IR intrinsics + DAG builder support
2018-07-16 22:59:31 +00:00
funnel-shift.ll
[Intrinsics] define funnel shift IR intrinsics + DAG builder support
2018-07-16 22:59:31 +00:00
ga-offset2.ll
…
ga-offset.ll
…
gather-addresses.ll
[X86] Remove some composite MOVSS/MOVSD isel patterns.
2018-07-11 04:51:40 +00:00
gcc_except_table_functions.ll
…
gcc_except_table.ll
…
gep-expanded-vector.ll
…
getelementptr.ll
…
gfni-intrinsics.ll
…
ghc-cc64.ll
…
ghc-cc.ll
…
global-access-pie-copyrelocs.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
global-access-pie.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
global-fill.ll
…
global-sections-comdat.ll
…
global-sections-tls.ll
…
global-sections.ll
[MachO] Emit Weak ReadOnlyWithRel to ConstDataSection
2018-04-10 20:16:35 +00:00
gnu-seh-nolpads.ll
…
gpr-to-mask.ll
[X86] Don't use EXTRACT_ELEMENT from v1i1 with i8/i32 result type when we need to guarantee zeroes in the upper bits of return.
2018-02-28 08:14:28 +00:00
greedy_regalloc_bad_eviction_sequence.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
gs-fold.ll
…
h-register-addressing-32.ll
…
h-register-addressing-64.ll
…
h-register-store.ll
…
h-registers-0.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
h-registers-1.ll
[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)
2018-05-01 19:51:15 +00:00
h-registers-2.ll
…
h-registers-3.ll
…
haddsub-2.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
haddsub-3.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
haddsub-shuf.ll
[X86][SSE] Use SplitOpsAndApply to improve HADD/HSUB lowering
2018-07-20 16:20:45 +00:00
haddsub-undef.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
haddsub.ll
…
half.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
handle-move.ll
…
hhvm-cc.ll
…
hidden-vis-2.ll
…
hidden-vis-3.ll
Use a got to access a hidden weak undefined on MachO.
2018-01-17 19:19:55 +00:00
hidden-vis-4.ll
…
hidden-vis-pic.ll
…
hidden-vis.ll
…
hipe-cc64.ll
Revert "Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models""
2018-06-28 17:56:43 +00:00
hipe-cc.ll
…
hipe-prologue.ll
…
hoist-common.ll
…
hoist-invariant-load.ll
…
hoist-spill-lpad.ll
…
hoist-spill.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
horizontal-reduce-smax.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
horizontal-reduce-smin.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
horizontal-reduce-umax.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
horizontal-reduce-umin.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
horizontal-shuffle.ll
…
huge-stack-offset2.ll
…
huge-stack-offset.ll
…
i1narrowfail.ll
…
i2k.ll
…
i16lshr8pat.ll
…
i64-mem-copy.ll
…
i64-to-float.ll
[SelectionDAG] ComputeNumSignBits - add support for SMIN+SMAX clamp patterns
2018-02-17 22:19:50 +00:00
i128-and-beyond.ll
…
i128-immediate.ll
…
i128-mul.ll
[CodeGen] Add a new pass for PostRA sink
2018-03-22 20:06:47 +00:00
i128-ret.ll
…
i128-sdiv.ll
…
i256-add.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
i386-setjmp-pic.ll
…
i386-shrink-wrapping.ll
[X86] Change some compare patterns to use loadi8/loadi16/loadi32/loadi64 helper fragments.
2018-02-12 02:48:42 +00:00
i386-tlscall-fastregalloc.ll
…
i486-fence-loop.ll
…
i686-win-shrink-wrapping.ll
…
iabs.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
icall-branch-funnel.ll
Use branch funnels for virtual calls when retpoline mitigation is enabled.
2018-03-09 19:11:44 +00:00
icmp-opt.ll
[DagCombiner] Not all 'andn''s work with immediates.
2018-05-07 21:52:11 +00:00
ident-metadata.ll
…
ifunc-asm.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
illegal-bitfield-loadstore.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
illegal-insert.ll
…
illegal-vector-args-return.ll
…
immediate_merging64.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
immediate_merging.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
implicit-null-check-negative.ll
…
implicit-null-check.ll
…
implicit-null-checks.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
implicit-null-chk-reg-rewrite.mir
[ImplicitNullChecks] Check for rewrite of register used in 'test' instruction
2018-07-04 08:01:26 +00:00
implicit-use-spill.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
imul-lea-2.ll
…
imul-lea.ll
…
imul.ll
[X86] Form MUL_IMM for multiplies with 3/5/9 to encourage LEA formation over load folding.
2018-04-25 17:35:03 +00:00
inalloca-ctor.ll
…
inalloca-invoke.ll
…
inalloca-regparm.ll
…
inalloca-stdcall.ll
…
inalloca.ll
…
inconsistent_landingpad.ll
…
indirect-branch-tracking.ll
[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
2018-05-18 11:58:25 +00:00
indirect-hidden.ll
…
init-priority.ll
…
inline-0bh.ll
…
inline-asm-2addr.ll
…
inline-asm-A-constraint.ll
Allow usage of X86-prefixes as separate instrs.
2018-01-17 10:12:06 +00:00
inline-asm-avx512f-v-constraint.ll
…
inline-asm-avx512vl-v-constraint-32bit.ll
…
inline-asm-avx512vl-v-constraint.ll
…
inline-asm-avx-v-constraint-32bit.ll
…
inline-asm-avx-v-constraint.ll
…
inline-asm-bad-constraint-n.ll
…
inline-asm-bad-modifier.ll
[X86] Don't crash on bad operand modifiers in inline assembly
2018-04-18 05:15:24 +00:00
inline-asm-duplicated-constraint.ll
…
inline-asm-error.ll
…
inline-asm-flag-clobber.ll
…
inline-asm-fpstack.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
inline-asm-h.ll
…
inline-asm-modifier-n.ll
…
inline-asm-modifier-q.ll
…
inline-asm-modifier-V.ll
[X86] Support 'V' register operand modifier
2018-02-08 20:06:05 +00:00
inline-asm-mrv.ll
…
inline-asm-out-regs.ll
…
inline-asm-pic.ll
…
inline-asm-ptr-cast.ll
…
inline-asm-q-regs.ll
…
inline-asm-R-constraint.ll
…
inline-asm-sp-clobber-memcpy.ll
…
inline-asm-stack-realign2.ll
…
inline-asm-stack-realign3.ll
…
inline-asm-stack-realign.ll
…
inline-asm-tied.ll
…
inline-asm-x-scalar.ll
…
inline-asm.ll
…
inline-sse.ll
…
inlineasm-sched-bug.ll
…
inreg.ll
[FastISel] Disable local value sinking by default
2018-04-11 16:03:07 +00:00
ins_split_regalloc.ll
…
ins_subreg_coalesce-1.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
ins_subreg_coalesce-2.ll
…
ins_subreg_coalesce-3.ll
…
insert-into-constant-vector.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
insert-positions.ll
…
insertelement-copytoregs.ll
…
insertelement-duplicates.ll
…
insertelement-legalize.ll
…
insertelement-ones.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
insertelement-shuffle.ll
[DAGCombiner] Add a DAG combine to turn a splat build_vector where the splat elemnt is a bitcast from a vector type into a concat_vector
2018-01-18 04:17:06 +00:00
insertelement-zero.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
insertps-combine.ll
…
insertps-from-constantpool.ll
…
insertps-O0-bug.ll
…
insertps-unfold-load-bug.ll
…
int-intrinsic.ll
…
interval-update-remat.ll
…
invalid-liveness.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
invalid-shift-immediate.ll
…
invpcid-intrinsic.ll
[x86] invpcid LLVM intrinsic
2018-05-25 06:32:05 +00:00
ipra-inline-asm.ll
[X86] Add phony registers for high halves of regs with low halves
2018-07-02 19:05:09 +00:00
ipra-local-linkage.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
ipra-reg-alias.ll
[X86] Add phony registers for high halves of regs with low halves
2018-03-20 18:46:55 +00:00
ipra-reg-usage.ll
[X86] Add phony registers for high halves of regs with low halves
2018-07-02 19:05:09 +00:00
ipra-transform.ll
…
isel-optnone.ll
…
isel-sink2.ll
…
isel-sink3.ll
…
isel-sink.ll
…
isint.ll
…
isnan2.ll
…
isnan.ll
…
ispositive.ll
…
jump_sign.ll
[X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just before isel to enable test instruction matching
2018-02-01 17:08:39 +00:00
known-bits-vector.ll
[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT
2018-07-17 09:45:35 +00:00
known-bits.ll
[x86] shrink 'and' immediate values by setting the high bits (PR35907)
2018-01-19 16:37:25 +00:00
known-signbits-vector.ll
[DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N)
2018-05-11 18:40:08 +00:00
label-annotation.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
label-redefinition.ll
…
lack-of-signed-truncation-check.ll
[NFC][X86][AArch64][DAGCombine] More tests for optimizeSetCCOfSignedTruncationCheck()
2018-07-18 16:19:06 +00:00
lakemont.ll
…
large-code-model-isel.ll
…
large-constants.ll
…
large-gep-chain.ll
…
large-gep-scale.ll
…
large-global.ll
…
late-address-taken.ll
[ShrinkWrap] Add optimization remarks to the shrink-wrapping pass
2018-06-05 00:27:24 +00:00
ldzero.ll
…
lea32-schedule.ll
[X86][BtVer2] correctly model the latency/throughput of LEA instructions.
2018-07-19 16:42:15 +00:00
lea64-schedule.ll
[X86][BtVer2] correctly model the latency/throughput of LEA instructions.
2018-07-19 16:42:15 +00:00
lea-2.ll
…
lea-3.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
lea-4.ll
…
lea-5.ll
…
lea-opt-cse1.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
lea-opt-cse2.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
lea-opt-cse3.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
lea-opt-cse4.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
lea-opt-memop-check-1.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
lea-opt-memop-check-2.ll
…
lea-opt-with-debug.mir
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
lea-opt.ll
…
lea-recursion.ll
…
lea.ll
…
leaf-fp-elim.ll
…
leaFixup32.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
leaFixup64.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
legalize-fmp-oeq-vector-select.ll
…
legalize-libcalls.ll
…
legalize-shift-64.ll
[X86] Limit the number of target specific nodes emitted in LowerShiftParts
2018-06-29 17:24:07 +00:00
legalize-shift.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
legalize-shl-vec.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
legalize-sub-zero-2.ll
…
legalize-sub-zero.ll
…
legalize-types-remapid.ll
[DAG] Don't map a TableId to itself in the ReplacedValues map
2018-06-20 16:06:09 +00:00
legalizedag_vec.ll
…
libcall-sret.ll
…
licm-dominance.ll
…
licm-nested.ll
…
licm-regpressure.ll
…
licm-symbol.ll
…
limit-split-cost.mir
[RegAlloc] Skip global splitting if the live range is huge and its spill is
2018-07-16 15:42:20 +00:00
limited-prec.ll
…
linux-preemption.ll
…
lit.local.cfg
…
live-out-reg-info.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
live-range-nosubreg.ll
…
liveness-local-regalloc.ll
…
llc-override-mcpu-mattr.ll
…
load-combine-dbg.ll
…
load-combine.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
load-slice.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
loadStore_vectorizer.ll
Reapply "[LSV] Refactoring + supporting bitcasts to a type of different size"
2018-07-20 20:10:04 +00:00
loc-remat.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
local_stack_symbol_ordering.ll
…
localescape.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
log2_not_readnone.ll
…
logical-load-fold.ll
…
long-setcc.ll
…
longlong-deadload.ll
…
loop-blocks.ll
…
loop-hoist.ll
…
loop-search.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
loop-strength-reduce2.ll
…
loop-strength-reduce4.ll
…
loop-strength-reduce5.ll
…
loop-strength-reduce6.ll
…
loop-strength-reduce7.ll
…
loop-strength-reduce8.ll
…
loop-strength-reduce-2.ll
…
loop-strength-reduce-3.ll
…
loop-strength-reduce-crash.ll
…
loop-strength-reduce.ll
…
lower-bitcast.ll
…
lower-vec-shift-2.ll
…
lower-vec-shift.ll
[X86][SSE] Prefer BLEND(SHL(v,c1),SHL(v,c2)) over MUL(v, c3)
2018-07-10 07:58:33 +00:00
lower-vec-shuffle-bug.ll
…
lrshrink.ll
…
lsr-crash-empty-uses.ll
Add a CHECK line for r337072.
2018-07-13 23:48:59 +00:00
lsr-delayed-fold.ll
…
lsr-i386.ll
…
lsr-interesting-step.ll
…
lsr-loop-exit-cond.ll
[X86][Atom] Convert Atom scheduler model to SchedRW (PR32431)
2018-04-11 18:23:01 +00:00
lsr-negative-stride.ll
…
lsr-nonaffine.ll
…
lsr-normalization.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
lsr-overflow.ll
…
lsr-quadratic-expand.ll
…
lsr-redundant-addressing.ll
…
lsr-reuse-trunc.ll
…
lsr-reuse.ll
…
lsr-sort.ll
…
lsr-static-addr.ll
[X86][Atom] Convert Atom scheduler model to SchedRW (PR32431)
2018-04-11 18:23:01 +00:00
lsr-wrap.ll
…
lwp-intrinsics-x86_64.ll
…
lwp-intrinsics.ll
…
lwp-schedule.ll
…
lzcnt-schedule.ll
Fix newlines. NFCI.
2018-03-26 21:07:59 +00:00
lzcnt-tzcnt.ll
[X86] Auto-generate checks. NFC
2018-02-06 18:18:49 +00:00
lzcnt-zext-cmp.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
lzcnt.ll
…
machine-combiner-int-vec.ll
[MachineCombiner] Add check for optimal pattern order.
2018-01-31 13:54:30 +00:00
machine-combiner-int.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
machine-combiner.ll
[MachineCombiner] Add check for optimal pattern order.
2018-01-31 13:54:30 +00:00
machine-copy-prop.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
machine-cp-debug.mir
[CodeGen] Ignore debug uses in MachineCopyPropagation
2018-07-11 13:30:27 +00:00
machine-cp.ll
[DAGCombine][X86][AArch64] Masked merge unfolding: vector edition.
2018-05-21 21:41:02 +00:00
machine-cse.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
machine-outliner-debuginfo.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
machine-outliner-disubprogram.ll
[MachineOutliner] Check the last instruction from the sequence when updating liveness
2018-07-14 09:40:01 +00:00
machine-outliner-noredzone.ll
[MachineOutliner] Test for X86FI->getUsesRedZone() as well as Attribute::NoRedZone
2018-04-03 23:32:41 +00:00
machine-outliner-tailcalls.ll
[MachineOutliner][NFC] Make outlined functions have internal linkage
2018-04-03 21:36:00 +00:00
machine-outliner.ll
[MachineOutliner][NFC] Make outlined functions have internal linkage
2018-04-03 21:36:00 +00:00
machine-region-info.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
machine-sink-and-implicit-null-checks.ll
…
machine-sink.ll
…
machine-trace-metrics-crash.ll
…
MachineBranchProb.ll
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
2018-02-09 00:10:31 +00:00
MachineSink-CritEdge.ll
…
MachineSink-DbgValue.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
MachineSink-eflags.ll
…
machinesink-merge-debuginfo.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
machinesink-null-debuginfo.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
MachineSink-PHIUse.ll
…
MachineSink-SubReg.ll
…
macho-comdat.ll
…
macho-trap.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
madd.ll
[X86][SSE] Use SplitOpsAndApply to improve HADD/HSUB lowering
2018-07-20 16:20:45 +00:00
mangle-question-mark.ll
[IR] Avoid the need to prefix MS C++ symbols with '\01'
2018-03-16 20:13:32 +00:00
mask-negated-bool.ll
…
masked_gather_scatter.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
masked_memop.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
masked-iv-safe.ll
…
masked-iv-unsafe.ll
…
maskmovdqu.ll
…
materialize.ll
…
mature-mc-support.ll
…
mbp-false-cfg-break.ll
…
mcinst-avx-lowering.ll
…
mcinst-lowering.ll
…
mcu-abi.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
mem-intrin-base-reg.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
mem-promote-integers.ll
…
membarrier.ll
…
memcmp-mergeexpand.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
memcmp-minsize.ll
…
memcmp-optsize.ll
[x86, MemCmpExpansion] allow 2 pairs of loads per block (PR33325)
2018-01-06 16:16:04 +00:00
memcmp.ll
[x86, MemCmpExpansion] allow 2 pairs of loads per block (PR33325)
2018-01-06 16:16:04 +00:00
memcpy-2.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
memcpy-from-string.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memcpy-struct-by-value.ll
…
memcpy.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
mempcpy-32.ll
…
mempcpy.ll
…
memset64-on-x86-32.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-2.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-3.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-nonzero.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
memset-sse-stack-realignment.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
merge_store_duplicated_loads.ll
…
merge_store.ll
…
merge-consecutive-loads-128.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
merge-consecutive-loads-256.ll
[X86] Remove patterns for inserting a load into a zero vector.
2018-07-11 18:09:04 +00:00
merge-consecutive-loads-512.ll
[X86] Fix some isel patterns that used aligned vector load instructions with unaligned predicates.
2018-03-08 00:21:17 +00:00
merge-consecutive-stores-i1.ll
…
merge-consecutive-stores.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
merge-sp-update-lea.ll
…
merge-sp-updates-cfi.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
merge-store-constants.ll
…
merge-store-partially-alias-loads.ll
[CodeGen] Use MIR syntax for MachineMemOperand printing
2018-03-14 21:52:13 +00:00
MergeConsecutiveStores.ll
…
mfence.ll
…
mingw-alloca.ll
…
mingw-comdats.ll
[X86] Fix 32-bit mingw comdat names, only add one underscore
2018-06-21 23:06:33 +00:00
misaligned-memset.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
misched-aa-colored.ll
…
misched-aa-mmos.ll
…
misched-balance.ll
…
misched-code-difference-with-debug.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
misched-copy.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
misched-crash.ll
…
misched-fusion.ll
…
misched-ilp.ll
…
misched-matmul.ll
…
misched-matrix.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
misched-new.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
mmx-arg-passing-x86-64.ll
…
mmx-arg-passing.ll
…
mmx-arith.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
mmx-bitcast-fold.ll
…
mmx-bitcast.ll
[X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead.
2018-01-05 20:55:12 +00:00
mmx-build-vector.ll
[X86] Remove some composite MOVSS/MOVSD isel patterns.
2018-07-11 04:51:40 +00:00
mmx-coalescing.ll
…
mmx-copy-gprs.ll
…
mmx-cvt.ll
[X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead.
2018-01-05 20:55:12 +00:00
mmx-fold-load.ll
[X86][MMX] Improve MMX constant generation
2018-01-16 14:21:28 +00:00
mmx-fold-zero.ll
[X86][MMX] Add support for MMX zero vector creation
2018-01-15 22:32:40 +00:00
mmx-intrinsics.ll
…
mmx-only.ll
…
mmx-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
mod128.ll
…
movbe-schedule.ll
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
2018-04-06 11:00:51 +00:00
movbe.ll
…
movdir-intrinsic-x86_64.ll
[X86] movdiri and movdir64b instructions
2018-05-01 10:01:16 +00:00
movdir-intrinsic-x86.ll
[X86] movdiri and movdir64b instructions
2018-05-01 10:01:16 +00:00
movfs.ll
…
movgs.ll
…
movmsk.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
movntdq-no-avx.ll
…
movpc32-check.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
movtopush64.ll
…
movtopush.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
movtopush.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
ms-inline-asm-avx512.ll
…
ms-inline-asm.ll
…
mul64.ll
…
mul128_sext_loop.ll
…
mul128.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
mul-constant-i16.ll
[X86] Form MUL_IMM for multiplies with 3/5/9 to encourage LEA formation over load folding.
2018-04-25 17:35:03 +00:00
mul-constant-i32.ll
[X86][BtVer2] correctly model the latency/throughput of LEA instructions.
2018-07-19 16:42:15 +00:00
mul-constant-i64.ll
[X86][BtVer2] correctly model the latency/throughput of LEA instructions.
2018-07-19 16:42:15 +00:00
mul-constant-result.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
mul-i256.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
mul-i512.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
mul-i1024.ll
[x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues.
2018-04-10 01:41:17 +00:00
mul-legalize.ll
…
mul-remat.ll
…
mul-shift-reassoc.ll
…
muloti.ll
…
mult-alt-generic-i686.ll
…
mult-alt-generic-x86_64.ll
…
mult-alt-x86.ll
…
multiple-loop-post-inc.ll
…
multiple-return-values-cross-block.ll
…
mulvi32.ll
[X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of lowering.
2018-04-07 19:09:52 +00:00
mulx32.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
mulx64.ll
…
musttail-fastcall.ll
…
musttail-indirect.ll
…
musttail-thiscall.ll
…
musttail-varargs.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
musttail.ll
…
mwaitx-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
mwaitx.ll
…
named-reg-alloc.ll
…
named-reg-notareg.ll
…
nancvt.ll
…
narrow_op-1.ll
…
narrow-shl-cst.ll
…
narrow-shl-load.ll
…
neg_cmp.ll
…
neg_fp.ll
…
neg-shl-add.ll
…
negate-add-zero.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
negate-i1.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
negate-shift.ll
…
negate.ll
…
negative_zero.ll
…
negative-offset.ll
…
negative-sin.ll
Go back to sometimes assuming intristics are local.
2018-03-10 02:42:14 +00:00
negative-stride-fptosi-user.ll
…
negative-subscript.ll
…
new-remat.ll
…
newline-and-quote.ll
…
no-and8ri8.ll
…
no-cmov.ll
…
no-plt-libcalls.ll
Simplification of libcall like printf->puts must check for RtLibUseGOT metadata.
2018-04-10 23:32:36 +00:00
no-plt.ll
GOTPCREL references must always use RIP.
2018-04-10 22:50:05 +00:00
no-prolog-kill.ll
…
no-sse2-avg.ll
…
no-stack-arg-probe.ll
Support for the mno-stack-arg-probe flag
2018-02-23 13:46:25 +00:00
nobt.ll
…
nocf_check.ll
[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
2018-05-18 11:58:25 +00:00
nocx16.ll
…
non-lazy-bind.ll
…
non-unique-sections.ll
…
non-value-mem-operand.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
nonconst-static-ev.ll
…
nonconst-static-iv.ll
…
nontemporal-2.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
nontemporal-loads.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
nontemporal.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
noreturn-call.ll
…
norex-subreg.ll
…
nosse-error1.ll
…
nosse-error2.ll
…
nosse-varargs.ll
…
nosse-vector.ll
…
not-and-simplify.ll
…
note-cet-property.ll
[X86][ELF][CET] Adding the .note.gnu.property ELF section in X86
2018-06-04 21:07:35 +00:00
note-sections.ll
…
null-streamer.ll
…
O0-pipeline.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
O3-pipeline.ll
[ShrinkWrap] Add optimization remarks to the shrink-wrapping pass
2018-06-05 00:27:24 +00:00
objc-gc-module-flags.ll
…
object-size.ll
…
oddshuffles.ll
[X86] Remove isel patterns for MOVSS/MOVSD ISD opcodes with integer types.
2018-07-20 17:57:53 +00:00
opaque-constant-asm.ll
…
opt_phis.mir
Move tests to the correct place
2018-01-19 06:08:15 +00:00
opt-ext-uses.ll
…
opt-shuff-tstore.ll
…
optimize-max-0.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
optimize-max-1.ll
…
optimize-max-2.ll
…
optimize-max-3.ll
…
or-address.ll
…
or-branch.ll
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
2018-02-23 11:50:42 +00:00
or-lea.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
osx-private-labels.ll
…
overflow-intrinsic-setcc-fold.ll
…
overflow.ll
…
overlap-shift.ll
…
packed_struct.ll
…
packss.ll
[Utils][X86] Help update_llc_test_checks.py to recognise retl/retq to reduce CHECK duplication (PR35003)
2018-06-01 13:37:01 +00:00
palignr.ll
…
partial-fold32.ll
…
partial-fold64.ll
…
pass-three.ll
…
patchable-prologue.ll
…
patchpoint-invoke.ll
Emit smaller exception tables for non-SJLJ mode.
2018-02-09 17:13:37 +00:00
patchpoint-verifiable.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
patchpoint-webkit_jscc.ll
…
patchpoint.ll
[CodeGen] fix argument attribute in lowering statepoint/patchpoint
2018-03-01 13:31:57 +00:00
pause.ll
…
peep-setb.ll
…
peep-test-0.ll
…
peep-test-1.ll
…
peep-test-2.ll
…
peep-test-3.ll
…
peep-test-4.ll
…
peephole-cvt-sse.ll
…
peephole-fold-movsd.ll
…
peephole-multiple-folds.ll
…
peephole-na-phys-copy-folding.ll
[x86] Switch EFLAGS copy lowering to use reg-reg form of testing for
2018-04-18 15:52:50 +00:00
peephole-recurrence.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
peephole.mir
…
personality_size.ll
…
personality.ll
…
phaddsub.ll
…
phi-bit-propagation.ll
…
phi-immediate-factoring.ll
…
phielim-split.ll
…
phys_subreg_coalesce-2.ll
…
phys_subreg_coalesce-3.ll
…
phys_subreg_coalesce.ll
…
phys-reg-local-regalloc.ll
…
pic_jumptable.ll
…
pic-load-remat.ll
…
pic.ll
…
pie.ll
…
pku.ll
[X86][PKU] Regenerate rdpkru/wrpkru intrinsic tests
2018-04-08 12:30:30 +00:00
pmovext.ll
…
pmovsx-inreg.ll
[DAGCombiner] Change the SDLoc on split extloads (2/N)
2018-05-01 19:29:15 +00:00
pmul.ll
[X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of lowering.
2018-04-07 19:09:52 +00:00
pmulh.ll
[X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 16) into PMULHW/PMULHUW.
2018-04-21 18:39:21 +00:00
pmulld.ll
…
pointer-vector.ll
…
pop-stack-cleanup-msvc.ll
…
pop-stack-cleanup.ll
…
popcnt-schedule.ll
Fix newlines. NFCI.
2018-03-26 21:07:59 +00:00
popcnt.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
post-ra-sched-with-debug.mir
[DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property
2018-06-21 10:03:34 +00:00
post-ra-sched.ll
…
postalloc-coalescing.ll
…
postra-ignore-dbg-instrs.mir
[DebugInfo] Ignore DBG_VALUE instructions in PostRA Machine Sink
2018-06-21 17:59:52 +00:00
postra-licm.ll
…
powi.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
pr1462.ll
…
pr1489.ll
…
pr1505.ll
…
pr1505b.ll
…
pr2177.ll
…
pr2182.ll
…
pr2326.ll
…
pr2585.ll
…
pr2656.ll
…
pr2659.ll
…
pr2849.ll
…
pr2924.ll
…
pr2982.ll
…
pr3154.ll
…
pr3216.ll
…
pr3241.ll
…
pr3243.ll
…
pr3244.ll
…
pr3250.ll
…
pr3317.ll
…
pr3366.ll
…
pr3457.ll
…
pr3522.ll
…
pr5145.ll
…
pr7882.ll
…
pr9127.ll
…
pr9743.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr10068.ll
…
pr10475.ll
…
pr10499.ll
…
pr10523.ll
…
pr10524.ll
…
pr10525.ll
…
pr10526.ll
…
pr11202.ll
…
pr11334.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
pr11415.ll
…
pr11468.ll
…
pr11985.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
pr11998.ll
…
pr12360.ll
[X86] Teach X86TargetLowering::targetShrinkDemandedConstant to set non-demanded bits if it helps created an and mask that can be matched as a zero extend.
2018-03-14 16:55:15 +00:00
pr12889.ll
…
pr13209.ll
…
pr13220.ll
…
pr13458.ll
…
pr13577.ll
[DAG] make binops with undef operands consistent with IR
2018-02-12 21:37:27 +00:00
pr13859.ll
…
pr13899.ll
…
pr14088.ll
[X86] Regenerate PR14088 test. NFCI.
2018-07-07 20:08:27 +00:00
pr14098.ll
…
pr14161.ll
…
pr14204.ll
…
pr14314.ll
…
pr14333.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
pr14562.ll
…
pr15267.ll
…
pr15296.ll
…
pr15309.ll
…
pr15705.ll
…
pr15981.ll
…
pr16031.ll
…
pr16360.ll
…
pr16807.ll
…
pr17546.ll
…
pr17631.ll
…
pr17764.ll
…
pr18014.ll
…
pr18054.ll
…
pr18162.ll
…
pr18344.ll
[X86][SSE] Don't colaesce v4i32 extracts
2018-01-26 17:11:34 +00:00
pr18846.ll
…
pr19049.ll
…
pr20011.ll
[SelectionDAG] Fix codegen of vector stores with non byte-sized elements.
2018-01-20 16:05:10 +00:00
pr20012.ll
…
pr20020.ll
…
pr20088.ll
…
pr21099.ll
…
pr21792.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr22019.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
pr22103.ll
…
pr22338.ll
…
pr22774.ll
…
pr22970.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pr23103.ll
Revert "Regenerate expected test results for test/CodeGen/X86/pr23103.ll . NFC"
2018-06-04 21:49:23 +00:00
pr23246.ll
[X86] Make all instructions that operate on MMX types, but were added after the initial MMX support via one of the SSE features flags make them require the MMX feature as well.
2018-06-05 06:20:06 +00:00
pr23273.ll
…
pr23603.ll
…
pr23664.ll
…
pr24139.ll
…
pr24374.ll
…
pr24602.ll
…
pr25828.ll
…
pr26350.ll
…
pr26625.ll
…
pr26652.ll
…
pr26757.ll
…
pr26835.ll
…
pr26870.ll
…
pr27071.ll
…
pr27501.ll
…
pr27591.ll
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
2018-03-01 22:32:25 +00:00
pr27681.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pr28129.ll
…
pr28173.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pr28444.ll
…
pr28472.ll
…
pr28489.ll
…
pr28504.ll
…
pr28515.ll
…
pr28560.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pr28824.ll
…
pr29010.ll
[NFC] fix trivial typos in comments
2018-04-13 11:37:06 +00:00
pr29022.ll
…
pr29061.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr29112.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
pr29170.ll
…
pr29222.ll
[X86][MMX] Support MMX build vectors to avoid SSE usage (PR29222)
2018-03-11 19:22:13 +00:00
pr30284.ll
…
pr30290.ll
[X86] Mark all byval parameters as aliased
2018-05-08 09:18:01 +00:00
pr30430.ll
[X86] Remove some composite MOVSS/MOVSD isel patterns.
2018-07-11 04:51:40 +00:00
pr30511.ll
…
pr30562.ll
…
pr30813.ll
…
pr30821.mir
Word wrap a test-file comment to 80 columns
2018-05-04 08:58:06 +00:00
pr31045.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
pr31088.ll
…
pr31143.ll
…
pr31242.ll
…
pr31271.ll
…
pr31323.ll
…
pr31593.ll
Added a testcase for PR31593. A patch (r291535) that fixed this bug didn't have a testcase.
2018-05-24 08:45:15 +00:00
pr31773.ll
…
pr31956.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
pr32108.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
pr32241.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr32256.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr32278.ll
…
pr32282.ll
[CodeGen] Emit more precise AssertZext/AssertSext nodes.
2018-07-11 23:26:35 +00:00
pr32284.ll
[DAGCombiner] Set the right SDLoc on extended SETCC uses (7/N)
2018-05-11 18:40:10 +00:00
pr32329.ll
Revert 336426 (and follow-ups 428, 440), it very likely caused PR38084.
2018-07-06 17:37:24 +00:00
pr32340.ll
[FastISel] Disable local value sinking by default
2018-04-11 16:03:07 +00:00
pr32345.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
pr32368.ll
…
pr32420.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
pr32451.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr32484.ll
[FastISel] Disable local value sinking by default
2018-04-11 16:03:07 +00:00
pr32515.ll
…
pr32588.ll
…
pr32610.ll
…
pr32659.ll
…
pr32907.ll
…
pr33290.ll
…
pr33349.ll
[X86] Lower extract_element from k-registers by bitcasting from v16i1 to i16 and extending/truncating.
2018-02-28 22:23:55 +00:00
pr33396.ll
…
pr33715.ll
…
pr33747.ll
[X86] Add PR33747 test case
2018-02-11 13:12:50 +00:00
pr33772.ll
…
pr33828.ll
…
pr33844.ll
[x86] shrink 'and' immediate values by setting the high bits (PR35907)
2018-01-19 16:37:25 +00:00
pr33954.ll
…
pr33960.ll
[DAG] make binops with undef operands consistent with IR
2018-02-12 21:37:27 +00:00
pr34080-2.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
pr34080.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
pr34088.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr34137.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
pr34139.ll
…
pr34149.ll
[DAG] propagate FMF for all FPMathOperators
2018-05-15 14:16:24 +00:00
pr34177.ll
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC
2018-06-04 22:09:26 +00:00
pr34271-1.ll
…
pr34271.ll
…
pr34381.ll
…
pr34397.ll
…
pr34421.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
pr34592.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr34605.ll
[X86] Use vmovdqu64/vmovdqa64 for unmasked integer vector stores for consistency with loads.
2018-01-18 07:44:09 +00:00
pr34629.ll
…
pr34634.ll
…
pr34653.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr34657.ll
…
pr34855.ll
…
pr35272.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
pr35316.ll
[X86] Rename function main->foo in CodeGen/X86/pr35316.ll. NFC
2018-02-13 10:58:19 +00:00
pr35399.ll
…
pr35443.ll
…
pr35636.ll
[X86] Add haswell testing for PR35635 as well.
2018-03-14 21:03:09 +00:00
pr35761.ll
[DAGCombine] Fix for PR35761
2018-01-08 13:21:24 +00:00
pr35763.ll
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
2018-03-01 22:32:25 +00:00
pr35765.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pr35918.ll
[X86][SSE] Add target shuffle support to X86TargetLowering::computeKnownBitsForTargetNode
2018-06-05 10:52:29 +00:00
pr35972.ll
[X86] When legalizing (v64i1 select i8, v64i1, v64i1) make sure not to introduce bitcasts to i64 in 32-bit mode
2018-01-17 18:46:01 +00:00
pr35982.ll
[X86][MMX] Add PR35982 test cases
2018-01-17 22:19:31 +00:00
pr36199.ll
[x86] preserve test intent by removing undef
2018-05-16 17:57:35 +00:00
pr36274.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
pr36312.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
pr36553.ll
[X86] Make sure we don't combine (fneg (fma X, Y, Z)) to a target specific node when there are no FMA instructions.
2018-03-01 00:08:38 +00:00
pr36602.ll
[DAG] Avoid using deleted node in rebuildSetCC
2018-05-10 14:28:54 +00:00
pr36865.ll
[DAG, X86] Fix ISel-time node insertion ids
2018-03-22 19:32:07 +00:00
pr37063.ll
[X86] Prevent folding loads with 64-bit ANDs with immediates that fit in 32-bits.
2018-04-10 03:44:15 +00:00
pr37264.ll
Follow-up to rL332176 by adding a test case for PR37264.
2018-05-13 14:32:23 +00:00
pr37359.ll
[SelectionDAG] Don't crash on inline assembly errors when the inline assembly return type is a struct.
2018-06-20 04:32:05 +00:00
pr37499.ll
[X86] Directly legalize v16i16/v8i16 vselect to vXi8 vselect to use VPBLENDVB
2018-05-18 17:48:06 +00:00
pr37820.ll
[DAG] Fix and-mask folding when narrowing loads.
2018-06-20 15:36:29 +00:00
pr37826.ll
[DAG] Fix Memory ordering check in ReduceLoadOpStore.
2018-07-20 15:20:50 +00:00
pr37879.ll
[X86] Remove the changes to combineScalarToVector made in r335037.
2018-06-25 00:21:53 +00:00
pr37916.ll
[ScheduleDAG] Fix unfolding of SUnits to already existent nodes.
2018-07-18 18:01:03 +00:00
pr38038.ll
Add x86_64-unkown triple to llc for x86 test.
2018-07-20 03:50:55 +00:00
pr38185.ll
[DAG] Avoid Node Update assertion due to AND simplification
2018-07-20 15:27:24 +00:00
PR34565.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
PR37310.mir
StackColoring: better handling of statically unreachable code
2018-05-29 13:52:24 +00:00
pre-coalesce-2.ll
…
pre-coalesce.ll
…
pre-coalesce.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pre-ra-sched.ll
…
prefer-avx256-lzcnt.ll
[X86] Teach X86 codegen to use vector width preference to avoid promoting to 512-bit types when VLX is enabled and the preference is for a smaller size.
2018-01-20 00:26:12 +00:00
prefer-avx256-mask-extend.ll
[X86][SSE] Consistently prefer lowering to PACKUS over PACKSS
2018-06-08 10:29:00 +00:00
prefer-avx256-mask-shuffle.ll
[X86][AVX] Use extract_subvector to reduce vector op widths (PR36761)
2018-07-19 21:52:06 +00:00
prefer-avx256-popcnt.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
prefer-avx256-shift.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
prefer-avx256-trunc.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
prefer-avx256-wide-mul.ll
[X86] Teach X86 codegen to use vector width preference to avoid promoting to 512-bit types when VLX is enabled and the preference is for a smaller size.
2018-01-20 00:26:12 +00:00
prefetch.ll
…
prefixdata.ll
…
preserve_allcc64.ll
…
preserve_mostcc64.ll
…
private-2.ll
…
private.ll
…
prolog-push-seq.ll
…
prologue-epilogue-remarks.mir
[PEI] Fix failing test caused by r324283
2018-02-05 23:06:47 +00:00
prologuedata.ll
…
promote-assert-zext.ll
…
promote-i16.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
promote-trunc.ll
…
promote-vec3.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
promote.ll
[X86][SSE] Aggressively use PMADDWD for v4i32 multiplies with 17 or more leading zeros
2018-01-24 19:20:02 +00:00
ps4-noreturn.ll
…
pseudo_cmov_lower1.ll
…
pseudo_cmov_lower2.ll
…
pseudo_cmov_lower.ll
…
pshufb-mask-comments.ll
…
pshufd-combine-crash.ll
…
psubus.ll
[X86][SSE] Simplify combineVectorTruncationWithPACKUS to reduce code duplication
2018-06-08 13:59:11 +00:00
ptest.ll
[X86] Add avx512 command line to ptest.ll to demonstrate that 512-bit vectors are not handled by LowerVectorAllZeroTest.
2018-02-02 20:12:45 +00:00
ptr-rotate.ll
…
ptrtoint-constexpr.ll
…
ptwrite32-intrinsic.ll
[X86] ptwrite intrinsic
2018-05-10 07:26:05 +00:00
ptwrite64-intrinsic.ll
[X86] ptwrite intrinsic
2018-05-10 07:26:05 +00:00
push-cfi-debug.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
push-cfi-obj.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
push-cfi.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
ragreedy-bug.ll
…
ragreedy-hoist-spill.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
ragreedy-last-chance-recoloring.ll
…
rd-mod-wr-eflags.ll
…
rdpid-schedule.ll
[X86] Split up -march=icelake to -client & -server
2018-04-10 18:59:13 +00:00
rdpid.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
rdpmc.ll
[X86] Regenerate RDPMC intrinsic test
2018-01-19 12:05:58 +00:00
rdrand-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
rdrand-x86_64.ll
…
rdrand.ll
[LoopStrengthReduce, x86] don't add cost for a cmp that will be macro-fused (PR35681)
2018-02-05 23:43:05 +00:00
rdseed-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
rdseed-x86_64.ll
…
rdseed.ll
…
rdtsc.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
read-fp-no-frame-pointer.ll
…
recip-fastmath2.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
recip-fastmath.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
recip-pic.ll
…
red-zone2.ll
…
red-zone.ll
…
reduce-trunc-shl.ll
[X86][SSE] Simplify combineVectorTruncationWithPACKSS to reduce code duplication
2018-06-07 13:01:42 +00:00
regalloc-advanced-split-cost.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
regalloc-reconcile-broken-hints.ll
…
regalloc-spill-at-ehpad.ll
…
regcall-no-plt.ll
…
reghinting.ll
…
regparm.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
regpressure.ll
…
rem_crash.ll
…
rem.ll
…
remat-constant.ll
…
remat-fold-load.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
remat-mov-0.ll
…
remat-phys-dead.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
remat-scalar-zero.ll
…
replace_unsupported_masked_mem_intrin.ll
[CodeGen] Do not allow opt-bisect-limit to skip ScalarizeMaskedMemIntrin.
2018-04-24 09:24:29 +00:00
replace-load-and-with-bzhi.ll
…
required-vector-width.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
ret-addr.ll
…
ret-i64-0.ll
…
ret-mmx.ll
…
retpoline-external.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
retpoline-regparm.ll
[X86] Use EDI for retpoline when no scratch regs are left
2018-02-13 20:47:49 +00:00
retpoline.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
return_zeroext_i2.ll
…
return-ext.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
returned-trunc-tail-calls.ll
…
reverse_branches.ll
…
rip-rel-address.ll
…
rip-rel-lea.ll
…
rodata-relocs.ll
…
rot16.ll
…
rot32.ll
…
rot64.ll
…
rotate2.ll
[X86] Regenerate rotate tests
2018-06-07 10:13:09 +00:00
rotate4.ll
[X86] Regenerate rotate tests
2018-06-07 10:13:09 +00:00
rotate_vec.ll
…
rotate-extract-vector.ll
[DAGCombiner] Add rotate-extract tests
2018-07-19 09:27:34 +00:00
rotate-extract.ll
[DAGCombiner] Add rotate-extract tests
2018-07-19 09:27:34 +00:00
rotate.ll
[X86] Regenerate rotate tests
2018-06-07 10:13:09 +00:00
rounding-ops.ll
[X86] Add isel patterns for folding loads when creating ROUND instructions from ffloor/fnearbyint/fceil/frint/ftrunc.
2018-06-12 00:48:57 +00:00
rrlist-livereg-corrutpion.ll
…
rtm-schedule.ll
[X86] Split up -march=icelake to -client & -server
2018-04-10 18:59:13 +00:00
rtm.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
sad_variations.ll
[X86][AVX] Add AVX1 PSAD tests
2018-02-26 15:55:25 +00:00
sad.ll
[X86][SSE] Use SplitOpsAndApply to improve HADD/HSUB lowering
2018-07-20 16:20:45 +00:00
saddo-redundant-add.ll
…
safestack_inline.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
safestack_ssp.ll
…
safestack.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
sandybridge-loads.ll
…
sar_fold64.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sar_fold.ll
…
sbb.ll
…
scalar_sse_minmax.ll
…
scalar_widen_div.ll
[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT
2018-07-17 09:45:35 +00:00
scalar-extract.ll
…
scalar-fp-to-i64.ll
[X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on 32-bit targets
2018-05-16 17:40:07 +00:00
scalar-int-to-fp.ll
[X86] Disable a DAG combine to allow packed AVX512DQ instructions to be consistently used for i64->float/double conversions.
2018-05-29 06:22:45 +00:00
scalar-min-max-fill-operand.ll
…
scalarize-bitcast.ll
…
scatter-schedule.ll
…
scavenger.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
scev-interchange.ll
…
schedule-x86_32.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
schedule-x86_64.ll
[X86] Add sched class WriteLAHFSAHF and fix values.
2018-06-20 06:13:39 +00:00
schedule-x86-64-shld.ll
[X86][BtVer2] correctly model the latency/throughput of LEA instructions.
2018-07-19 16:42:15 +00:00
scheduler-backtracking.ll
…
sdiv-exact.ll
…
sdiv-pow2.ll
…
segmented-stacks-dynamic.ll
…
segmented-stacks.ll
[X86,ARM] Retain split-stack prolog check for sibling calls
2018-06-26 14:11:30 +00:00
seh-catch-all-win32.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
seh-catch-all.ll
…
seh-catchpad.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
seh-except-finally.ll
…
seh-exception-code.ll
…
seh-filter-no-personality.ll
…
seh-finally.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
seh-no-invokes.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
seh-safe-div-win32.ll
…
seh-safe-div.ll
…
seh-stack-realign.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
select_const.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
select_meta.ll
…
select-1-or-neg1.ll
[x86] add select test to show there's no single right answer (PR28968); NFC
2018-02-12 22:19:24 +00:00
select-mmx.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
select-with-and-or.ll
…
select.ll
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
2018-07-15 16:27:07 +00:00
selectcc-to-shiftand.ll
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
2018-07-15 16:27:07 +00:00
selectiondag-crash.ll
…
selectiondag-cse.ll
…
selectiondag-debug-loc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
selectiondag-dominator.ll
…
selectiondag-order.ll
…
setcc-combine.ll
…
setcc-logic.ll
…
setcc-lowering.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
setcc-narrowing.ll
…
setcc-wide-types.ll
…
setcc.ll
…
setjmp-spills.ll
…
setoeq.ll
…
setuge.ll
…
sext-i1.ll
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
2018-03-01 22:32:25 +00:00
sext-load.ll
…
sext-ret-val.ll
…
sext-setcc-self.ll
…
sext-subreg.ll
…
sext-trunc.ll
…
sha-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
sha.ll
…
shadow-call-stack.mir
ShadowCallStack/x86_64: Ignore pseudo-machine instructions
2018-04-10 01:31:01 +00:00
shadow-stack.ll
SelectionDAGBuilder, mach-o: Skip trap after noreturn call (for Mach-O)
2018-06-28 17:00:45 +00:00
shift-and.ll
…
shift-avx2-crash.ll
…
shift-bmi2.ll
…
shift-coalesce.ll
…
shift-codegen.ll
…
shift-combine-crash.ll
…
shift-combine.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
shift-double-x86_64.ll
…
shift-double.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
shift-folding.ll
…
shift-i128.ll
…
shift-i256.ll
…
shift-one.ll
…
shift-pair.ll
[X86] Teach X86DAGToDAGISel::shrinkAndImmediate to preserve upper 32 zeroes of a 64 bit mask.
2018-02-05 16:54:07 +00:00
shift-parts.ll
…
shift-pcmp.ll
…
shl_elim.ll
…
shl_undef.ll
…
shl-anyext.ll
…
shl-crash-on-legalize.ll
…
shl-i64.ll
…
shrink_vmul_sse.ll
…
shrink_vmul.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
shrink_wrap_dbg_value.mir
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
shrink-compare.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
shrink-fp-const1.ll
…
shrink-fp-const2.ll
…
shrink-wrap-chkstk-x86_64.ll
[X86] Handle EAX being live when calling chkstk for x86_64
2018-03-06 06:00:13 +00:00
shrink-wrap-chkstk.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
shrink-wrapping-vla.ll
Add tests for shrink wrapping and VLAs
2018-04-18 13:37:12 +00:00
shrinkwrap-hang.ll
…
shuffle-combine-crash-2.ll
…
shuffle-combine-crash.ll
…
shuffle-of-insert.ll
…
shuffle-of-splat-multiuses.ll
X86 Tests: Update more isel tests with FastVariableShuffle feature
2018-01-09 16:26:06 +00:00
shuffle-strided-with-offset-128.ll
X86 Tests: Update more isel tests with FastVariableShuffle feature
2018-01-09 16:26:06 +00:00
shuffle-strided-with-offset-256.ll
X86 Tests: Update more isel tests with FastVariableShuffle feature
2018-01-09 16:26:06 +00:00
shuffle-strided-with-offset-512.ll
[X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads.
2018-01-18 07:44:06 +00:00
shuffle-vs-trunc-128.ll
[X86][AVX512] Add VBMI target shuffle-trunc tests
2018-01-30 16:01:41 +00:00
shuffle-vs-trunc-256.ll
[x86] Lower some trunc + shuffle patterns to vpmov[q|d][b|w]
2018-06-21 14:16:45 +00:00
shuffle-vs-trunc-512.ll
[x86] Lower some trunc + shuffle patterns to vpmov[q|d][b|w]
2018-06-21 14:16:45 +00:00
sibcall-2.ll
…
sibcall-3.ll
…
sibcall-4.ll
…
sibcall-5.ll
…
sibcall-6.ll
…
sibcall-byval.ll
…
sibcall-win64.ll
…
sibcall.ll
[x86] auto-generate checks; NFC
2018-04-20 16:46:58 +00:00
signbit-shift.ll
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
2018-07-15 16:27:07 +00:00
signed-truncation-check.ll
[NFC][X86][AArch64][DAGCombine] More tests for optimizeSetCCOfSignedTruncationCheck()
2018-07-18 16:19:06 +00:00
simple-register-allocation-read-undef.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
simple-zext.ll
…
sincos-opt.ll
…
sincos.ll
…
sink-blockfreq.ll
…
sink-cheap-instructions.ll
…
sink-gep-before-mem-inst.ll
…
sink-hoist.ll
…
sink-local-value.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
sink-out-of-loop.ll
…
sitofp.ll
[X86] Fix missing cfi from sitofp checks
2018-04-24 13:24:56 +00:00
sjlj-baseptr.ll
…
sjlj-eh.ll
…
sjlj.ll
…
slow-incdec.ll
…
slow-pmulld.ll
[X86] Revert the SLM part of r328914.
2018-04-09 17:07:40 +00:00
slow-unaligned-mem.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
small-byval-memcpy.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
smul-with-overflow.ll
…
soft-fp-legal-in-HW-reg.ll
…
soft-fp.ll
…
soft-sitofp.ll
…
speculative-load-hardening-gather.ll
[x86/SLH] Teach speculative load hardening to correctly harden the
2018-07-16 04:17:51 +00:00
speculative-load-hardening.ll
[x86/SLH] Flesh out the data-invariant instruction table a bit based on feedback from Craig.
2018-07-17 18:07:59 +00:00
splat-const.ll
…
splat-for-size.ll
…
split-eh-lpad-edges.ll
…
split-extend-vector-inreg.ll
[SelectionDAG] Add initial implementation of TargetLowering::SimplifyDemandedVectorElts
2018-02-15 12:14:15 +00:00
split-store.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
split-vector-bitcast.ll
…
split-vector-rem.ll
…
sqrt-fastmath-mir.ll
propagate fast math flags via IR on fma and sub expressions
2018-06-07 22:49:09 +00:00
sqrt-fastmath-tune.ll
…
sqrt-fastmath.ll
[X86] Enable reciprocal estimates for v16f32 vectors by using VRCP14PS/VRSQRT14PS
2018-05-06 17:48:21 +00:00
sqrt-partial.ll
…
sqrt.ll
…
sret-implicit.ll
…
sse1.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
sse2-intrinsics-fast-isel-x86_64.ll
[X86][SSE] Cleanup SSE2 intrinsics tests
2018-06-02 19:43:14 +00:00
sse2-intrinsics-fast-isel.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
sse2-intrinsics-x86_64-upgrade.ll
[X86][SSE] Cleanup SSE2 intrinsics tests
2018-06-02 19:43:14 +00:00
sse2-intrinsics-x86_64.ll
[X86][SSE] Cleanup SSE2 intrinsics tests
2018-06-02 19:43:14 +00:00
sse2-intrinsics-x86-upgrade.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
sse2-intrinsics-x86.ll
[X86] Lowering sqrt intrinsics to native IR
2018-06-15 18:05:24 +00:00
sse2-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
sse2-vector-shifts.ll
…
sse2.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
sse3-avx-addsub-2.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
sse3-avx-addsub.ll
…
sse3-intrinsics-fast-isel.ll
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
2018-06-02 18:41:46 +00:00
sse3-intrinsics-x86.ll
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
2018-06-02 18:41:46 +00:00
sse3-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
sse3.ll
[SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying shuffle masks
2018-02-16 16:22:14 +00:00
sse4a-intrinsics-fast-isel.ll
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests
2018-06-02 17:33:26 +00:00
sse4a-schedule.ll
[X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes
2018-05-03 13:27:10 +00:00
sse4a-upgrade.ll
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests
2018-06-02 17:33:26 +00:00
sse4a.ll
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests
2018-06-02 17:33:26 +00:00
sse41-intrinsics-fast-isel.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
sse41-intrinsics-x86-upgrade.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
sse41-intrinsics-x86.ll
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing
2018-06-02 18:01:09 +00:00
sse41-pmovxrm.ll
…
sse41-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
sse41.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
sse42-intrinsics-fast-isel-x86_64.ll
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing
2018-06-02 18:01:09 +00:00
sse42-intrinsics-fast-isel.ll
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing
2018-06-02 18:01:09 +00:00
sse42-intrinsics-x86_64.ll
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing
2018-06-02 18:01:09 +00:00
sse42-intrinsics-x86.ll
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing
2018-06-02 18:01:09 +00:00
sse42-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
sse_partial_update.ll
[X86] Lowering sqrt intrinsics to native IR
2018-06-15 18:05:24 +00:00
sse_reload_fold.ll
…
sse-align-0.ll
…
sse-align-1.ll
…
sse-align-2.ll
…
sse-align-3.ll
…
sse-align-4.ll
…
sse-align-5.ll
…
sse-align-6.ll
…
sse-align-7.ll
…
sse-align-8.ll
…
sse-align-9.ll
…
sse-align-10.ll
…
sse-align-11.ll
…
sse-align-12.ll
…
sse-commute.ll
…
sse-cvttp2si.ll
[DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros
2018-06-27 18:16:40 +00:00
sse-domains.ll
…
sse-fcopysign.ll
[X86] Remove some composite MOVSS/MOVSD isel patterns.
2018-07-11 04:51:40 +00:00
sse-fsignum.ll
[X86] Extend inputs with elements smaller than i32 to sint_to_fp/uint_to_fp before type legalization.
2018-02-10 17:58:58 +00:00
sse-intel-ocl.ll
…
sse-intrinsics-fast-isel-x86_64.ll
[X86][SSE] Cleanup SSE1 intrinsics tests
2018-06-02 20:25:56 +00:00
sse-intrinsics-fast-isel.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
sse-intrinsics-x86_64-upgrade.ll
[X86][SSE] Cleanup SSE1 intrinsics tests
2018-06-02 20:25:56 +00:00
sse-intrinsics-x86_64.ll
[X86][SSE] Cleanup SSE1 intrinsics tests
2018-06-02 20:25:56 +00:00
sse-intrinsics-x86-upgrade.ll
[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions.
2018-07-12 22:14:10 +00:00
sse-intrinsics-x86.ll
[X86] Lowering sqrt intrinsics to native IR
2018-06-15 18:05:24 +00:00
sse-load-ret.ll
…
sse-minmax.ll
…
sse-only.ll
…
sse-regcall.ll
…
sse-scalar-fp-arith-unary.ll
[X86][SSE] Cleanup SSE1 intrinsics tests
2018-06-02 20:25:56 +00:00
sse-scalar-fp-arith.ll
[X86][SSE] Canonicalize scalar fp arithmetic shuffle patterns
2018-07-18 19:55:19 +00:00
sse-schedule.ll
[X86] Fix NOOP sched overrides on BDW/HSW/SKL.
2018-06-18 06:48:22 +00:00
sse-unaligned-mem-feature.ll
…
sse-varargs.ll
…
ssp-data-layout.ll
…
ssp-guard-spill.ll
…
ssse3-intrinsics-fast-isel.ll
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
2018-06-02 18:41:46 +00:00
ssse3-intrinsics-x86.ll
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
2018-06-02 18:41:46 +00:00
ssse3-schedule.ll
[X86] Fix skylake server scheduling info.
2018-06-11 14:37:53 +00:00
stack_guard_remat.ll
…
stack-align2.ll
…
stack-align-memcpy.ll
…
stack-align.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
stack-folding-3dnow.ll
…
stack-folding-adx-x86_64.ll
…
stack-folding-bmi2.ll
…
stack-folding-bmi.ll
…
stack-folding-fp-avx1.ll
[X86] Go through some tests that still reference old intrinsics that have been autoupgraded and replace them with the upgraded IR.
2018-06-21 06:17:16 +00:00
stack-folding-fp-avx512.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
stack-folding-fp-avx512vl.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
stack-folding-fp-sse42.ll
[X86] Go through some tests that still reference old intrinsics that have been autoupgraded and replace them with the upgraded IR.
2018-06-21 06:17:16 +00:00
stack-folding-int-avx1.ll
[X86] Go through some tests that still reference old intrinsics that have been autoupgraded and replace them with the upgraded IR.
2018-06-21 06:17:16 +00:00
stack-folding-int-avx2.ll
[X86] Go through some tests that still reference old intrinsics that have been autoupgraded and replace them with the upgraded IR.
2018-06-21 06:17:16 +00:00
stack-folding-int-avx512.ll
[X86] Go through some tests that still reference old intrinsics that have been autoupgraded and replace them with the upgraded IR.
2018-06-21 06:17:16 +00:00
stack-folding-int-avx512vl.ll
[X86] Go through some tests that still reference old intrinsics that have been autoupgraded and replace them with the upgraded IR.
2018-06-21 06:17:16 +00:00
stack-folding-int-sse42.ll
[X86] Go through some tests that still reference old intrinsics that have been autoupgraded and replace them with the upgraded IR.
2018-06-21 06:17:16 +00:00
stack-folding-lwp.ll
…
stack-folding-mmx.ll
…
stack-folding-sha.ll
…
stack-folding-tbm.ll
[X86][TBM] Use realistic BEXTR control bits
2018-06-03 18:15:06 +00:00
stack-folding-x86_64.ll
…
stack-folding-xop.ll
…
stack-probe-red-zone.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
stack-probe-size.ll
…
stack-probes.ll
…
stack-protector-dbginfo.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
stack-protector-msvc.ll
…
stack-protector-remarks.ll
…
stack-protector-target.ll
…
stack-protector-vreg-to-vreg-copy.ll
…
stack-protector-weight.ll
[CodeGen] Use MIR syntax for MachineMemOperand printing
2018-03-14 21:52:13 +00:00
stack-protector.ll
[StackProtector] Ignore certain intrinsics when calculating sspstrong heuristic.
2018-04-06 20:14:13 +00:00
stack-size-section-function-sections.ll
Recommit r335333 "[MC] - Add .stack_size sections into groups and link them with .text"
2018-06-22 10:53:47 +00:00
stack-size-section.ll
Recommit r335333 "[MC] - Add .stack_size sections into groups and link them with .text"
2018-06-22 10:53:47 +00:00
stack-update-frame-opcode.ll
…
StackColoring-dbg.ll
…
StackColoring.ll
…
stackguard-internal.ll
…
stackmap-fast-isel.ll
…
stackmap-frame-setup.ll
…
stackmap-large-constants.ll
…
stackmap-large-location-size.ll
…
stackmap-liveness.ll
…
stackmap-nops.ll
…
stackmap-shadow-optimization.ll
…
stackmap.ll
…
stackpointer.ll
…
statepoint-allocas.ll
…
statepoint-call-lowering.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
statepoint-far-call.ll
…
statepoint-forward.ll
…
statepoint-gctransition-call-lowering.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
statepoint-invoke.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
statepoint-live-in.ll
Revert change 335077 "[InlineSpiller] Fix a crash due to lack of forward progress from remat specifically for STATEPOINT"
2018-06-25 12:58:13 +00:00
statepoint-stack-usage.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
statepoint-stackmap-format.ll
…
statepoint-uniqueing.ll
…
statepoint-vector-bad-spill.ll
…
statepoint-vector.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
stdarg.ll
…
stdcall-notailcall.ll
…
stdcall.ll
…
store_op_load_fold2.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
store_op_load_fold.ll
…
store-empty-member.ll
…
store-fp-constant.ll
…
store-global-address.ll
…
store-narrow.ll
…
store-zero-and-minus-one.ll
…
stores-merging.ll
…
storetrunc-fp.ll
…
stride-nine-with-base-reg.ll
…
stride-reuse.ll
…
sttni.ll
[X86][SSE] Remove unnecessary -cpu from sttni tests
2018-05-30 14:11:57 +00:00
sub-with-overflow.ll
…
sub.ll
…
subcarry.ll
[DAGcombine] Teach the combiner about -a = ~a + 1
2018-06-04 19:23:22 +00:00
subreg-to-reg-0.ll
…
subreg-to-reg-1.ll
…
subreg-to-reg-2.ll
…
subreg-to-reg-3.ll
…
subreg-to-reg-4.ll
…
subreg-to-reg-6.ll
…
subvector-broadcast.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
sunkaddr-ext.ll
…
swift-error.ll
…
swift-return.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
swiftcc.ll
…
swifterror.ll
…
swiftself.ll
…
switch-bt.ll
…
switch-crit-edge-constant.ll
…
switch-default-only.ll
…
switch-density.ll
…
switch-edge-weight.ll
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
2018-02-09 00:10:31 +00:00
switch-jump-table.ll
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
2018-02-09 00:10:31 +00:00
switch-lower-peel-top-case.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
switch-or.ll
…
switch-order-weight.ll
…
switch-zextload.ll
…
switch.ll
…
SwitchLowering.ll
…
swizzle-2.ll
…
swizzle-avx2.ll
…
SwizzleShuff.ll
…
system-intrinsics-64-xsave.ll
…
system-intrinsics-64-xsavec.ll
…
system-intrinsics-64-xsaveopt.ll
…
system-intrinsics-64-xsaves.ll
…
system-intrinsics-64.ll
…
system-intrinsics-xgetbv.ll
…
system-intrinsics-xsave.ll
…
system-intrinsics-xsavec.ll
…
system-intrinsics-xsaveopt.ll
…
system-intrinsics-xsaves.ll
…
system-intrinsics-xsetbv.ll
…
system-intrinsics.ll
…
tail-call-attrs.ll
…
tail-call-casts.ll
…
tail-call-conditional.mir
[X86] Add phony registers for high halves of regs with low halves
2018-07-02 19:05:09 +00:00
tail-call-got.ll
…
tail-call-legality.ll
…
tail-call-mutable-memarg.ll
…
tail-call-parameter-attrs-mismatch.ll
…
tail-call-win64.ll
…
tail-dup-addr.ll
…
tail-dup-catchret.ll
…
tail-dup-debugloc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
tail-dup-merge-loop-headers.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
tail-dup-no-other-successor.ll
…
tail-dup-repeat.ll
…
tail-merge-after-mbp.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
tail-merge-debugloc.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
tail-merge-identical.ll
…
tail-merge-unreachable.ll
…
tail-merge-wineh.ll
…
tail-opts.ll
…
tail-threshold.ll
…
tailcall-64.ll
…
tailcall-calleesave.ll
…
tailcall-cgp-dup.ll
…
tailcall-disable.ll
…
tailcall-fastisel.ll
…
tailcall-largecode.ll
…
tailcall-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
tailcall-msvc-conventions.ll
…
tailcall-multiret.ll
…
tailcall-readnone.ll
…
tailcall-returndup-void.ll
…
tailcall-ri64.ll
…
tailcall-stackalign.ll
…
tailcall-structret.ll
…
tailcall.ll
…
tailcallbyval64.ll
…
tailcallbyval.ll
…
tailcallfp2.ll
…
tailcallfp.ll
…
tailcallpic1.ll
…
tailcallpic2.ll
…
tailcallpic3.ll
…
tailcallstack64.ll
…
taildup-crash.ll
…
tailjmp_gotpcrel_relax_relocation.ll
Relax GOTPCREL relocations for tail jmp instructions.
2018-05-31 18:12:33 +00:00
targetLoweringGeneric.ll
…
tbm_patterns.ll
[DAGCombiner] Add one use check to fold (not (and x, y)) -> (or (not x), (not y))
2018-02-13 16:25:27 +00:00
tbm-intrinsics-fast-isel-x86_64.ll
[X86][TBM] Use realistic BEXTR control bits
2018-06-03 18:15:06 +00:00
tbm-intrinsics-fast-isel.ll
[X86][TBM] Use realistic BEXTR control bits
2018-06-03 18:15:06 +00:00
tbm-intrinsics-x86_64.ll
[X86][BMI][TBM] Only demand bottom 16-bits of the BEXTR control op (PR34042)
2018-06-06 10:52:10 +00:00
tbm-intrinsics.ll
[X86][TBM] Use realistic BEXTR control bits
2018-06-03 18:15:06 +00:00
tbm-schedule.ll
[X86] Don't hardcode scheduler class
2018-05-27 14:54:18 +00:00
test-nofold.ll
…
test-shrink-bug.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
test-shrink.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
test-vs-bittest.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
testb-je-fusion.ll
[X86] Avoid using high register trick for test instruction
2018-01-31 16:48:54 +00:00
testl-commute.ll
…
this-return-64.ll
…
throws-cfi-fp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
throws-cfi-no-fp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
tls-addr-non-leaf-function.ll
…
tls-android-negative.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
tls-android.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
tls-local-dynamic.ll
…
tls-models.ll
…
tls-pic.ll
…
tls-pie.ll
…
tls-shrink-wrapping.ll
…
tls-windows-itanium.ll
…
tls.ll
…
tlv-1.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
tlv-2.ll
…
tlv-3.ll
…
token_landingpad.ll
…
trap.ll
…
trunc-ext-ld-st.ll
…
trunc-store.ll
[SelectionDAG] Fix codegen of vector stores with non byte-sized elements.
2018-01-20 16:05:10 +00:00
trunc-subvector.ll
[X86][AVX] Use extract_subvector to reduce vector op widths (PR36761)
2018-07-19 21:52:06 +00:00
trunc-to-bool.ll
…
TruncAssertSext.ll
…
TruncAssertZext.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
twoaddr-coalesce-2.ll
…
twoaddr-coalesce-3.ll
…
twoaddr-coalesce.ll
…
twoaddr-lea.ll
…
twoaddr-pass-sink.ll
…
twoaddr-sink-terminator.ll
…
uint64-to-float.ll
…
uint_to_fp-2.ll
…
uint_to_fp-3.ll
…
uint_to_fp.ll
…
umul-with-carry.ll
…
umul-with-overflow.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
unaligned-32-byte-memops.ll
…
unaligned-load.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
unaligned-spill-folding.ll
…
undef-globals-bss.ll
Place undefined globals in .bss instead of .data
2018-02-06 23:22:14 +00:00
undef-label.ll
[x86] fix test to be independent of FP undef
2018-03-08 17:24:30 +00:00
undef-ops.ll
[DAG] fix type of undef returned by getNode()
2018-02-13 14:55:07 +00:00
unfold-masked-merge-scalar-constmask-innerouter.ll
[X86][AArch64][NFC] Add tests for masked merge unfolding
2018-04-23 20:38:42 +00:00
unfold-masked-merge-scalar-constmask-interleavedbits.ll
[X86][AArch64][NFC] Add tests for masked merge unfolding
2018-04-23 20:38:42 +00:00
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
[X86][AArch64][NFC] Add tests for masked merge unfolding
2018-04-23 20:38:42 +00:00
unfold-masked-merge-scalar-constmask-lowhigh.ll
[X86][AArch64][NFC] Add tests for masked merge unfolding
2018-04-23 20:38:42 +00:00
unfold-masked-merge-scalar-variablemask.ll
[DAGCombiner] Masked merge: enhance handling of 'andn' with immediates
2018-05-07 21:52:22 +00:00
unfold-masked-merge-vector-variablemask-const.ll
[DAGCombiner] isAllOnesConstantOrAllOnesSplatConstant(): look through bitcasts
2018-05-21 21:41:10 +00:00
unfold-masked-merge-vector-variablemask.ll
[DAGCombine][X86][AArch64] Masked merge unfolding: vector edition.
2018-05-21 21:41:02 +00:00
unknown-location.ll
…
unreachable-loop-sinking.ll
…
unreachable-mbb-undef-phi.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
unreachable-trap.ll
SelectionDAGBuilder, mach-o: Skip trap after noreturn call (for Mach-O)
2018-06-28 17:00:45 +00:00
unreachableblockelim.ll
…
unused_stackslots.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
unwind-init.ll
…
unwindraise.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
update-terminator-debugloc.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
update-terminator.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
urem-i8-constant.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
urem-power-of-two.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
use-add-flags.ll
…
utf8.ll
…
utf16-cfstrings.ll
…
v2f32.ll
…
v4f32-immediate.ll
…
v4i32load-crash.ll
…
v8i1-masks.ll
…
vaargs.ll
…
vaes-intrinsics-avx512-x86.ll
…
vaes-intrinsics-avx512vl-x86.ll
…
vaes-intrinsics-avx-x86.ll
…
var-permute-128.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
var-permute-256.ll
[X86][AVX512] Added more non-VLX test cases
2018-03-11 18:28:37 +00:00
var-permute-512.ll
…
vararg_no_start.ll
…
vararg_tailcall.ll
…
vararg-callee-cleanup.ll
…
variable-sized-darwin-bzero.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
variadic-node-pic.ll
…
vastart-defs-eflags.ll
[X86] Avoid using high register trick for test instruction
2018-01-31 16:48:54 +00:00
vbinop-simplify-bug.ll
…
vec3.ll
…
vec_add.ll
…
vec_align_i256.ll
…
vec_align.ll
…
vec_anyext.ll
…
vec_call.ll
…
vec_cast2.ll
[X86][SSE] Replace -cpu with equivalent -mattr for vec_cast tests
2018-05-30 14:01:21 +00:00
vec_cast3.ll
[X86][SSE] Replace -cpu with equivalent -mattr for vec_cast tests
2018-05-30 14:01:21 +00:00
vec_cast.ll
[X86][SSE] Replace -cpu with equivalent -mattr for vec_cast tests
2018-05-30 14:01:21 +00:00
vec_cmp_sint-128.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_cmp_uint-128.ll
[X86] Use min/max for vector ult/ugt compares if avoids a sign flip.
2018-02-11 17:11:40 +00:00
vec_compare-sse4.ll
…
vec_compare.ll
…
vec_ctbits.ll
…
vec_ext_inreg.ll
…
vec_extract-avx.ll
[X86] Use 128-bit ops for 256-bit vzmovl patterns.
2018-07-15 18:51:07 +00:00
vec_extract-mmx.ll
…
vec_extract-sse4.ll
…
vec_extract.ll
…
vec_fabs.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vec_floor.ll
[X86] Don't fold unaligned loads into SSE ROUNDPS/ROUNDPD for ceil/floor/nearbyint/rint/trunc.
2018-06-19 17:51:42 +00:00
vec_fneg.ll
…
vec_fp_to_int.ll
[x86] preserve test intent by removing undef
2018-05-17 18:43:44 +00:00
vec_fpext.ll
[X86][AVX] Use extract_subvector to reduce vector op widths (PR36761)
2018-07-19 21:52:06 +00:00
vec_fptrunc.ll
…
vec_i64.ll
…
vec_ins_extract-1.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_ins_extract.ll
…
vec_insert-2.ll
…
vec_insert-3.ll
…
vec_insert-4.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_insert-5.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_insert-7.ll
[TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts
2018-03-06 22:32:01 +00:00
vec_insert-8.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_insert-9.ll
…
vec_insert-mmx.ll
[X86][MMX] Support MMX build vectors to avoid SSE usage (PR29222)
2018-03-11 19:22:13 +00:00
vec_int_to_fp.ll
[X86][AVX] Use extract_subvector to reduce vector op widths (PR36761)
2018-07-19 21:52:06 +00:00
vec_loadsingles.ll
…
vec_logical.ll
…
vec_minmax_match.ll
[X86] Use min/max for vector ult/ugt compares if avoids a sign flip.
2018-02-11 17:11:40 +00:00
vec_minmax_sint.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
vec_minmax_uint.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
vec_partial.ll
…
vec_reassociate.ll
…
vec_return.ll
…
vec_round.ll
…
vec_sdiv_to_shift.ll
…
vec_set-2.ll
…
vec_set-3.ll
…
vec_set-4.ll
…
vec_set-6.ll
…
vec_set-7.ll
…
vec_set-8.ll
…
vec_set-A.ll
…
vec_set-B.ll
…
vec_set-C.ll
…
vec_set-D.ll
…
vec_set-F.ll
…
vec_set-H.ll
…
vec_set.ll
…
vec_setcc-2.ll
[X86] Use min/max for vector ult/ugt compares if avoids a sign flip.
2018-02-11 17:11:40 +00:00
vec_setcc.ll
…
vec_shift2.ll
…
vec_shift3.ll
…
vec_shift4.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
vec_shift5.ll
…
vec_shift6.ll
[X86][SSE] Prefer BLEND(SHL(v,c1),SHL(v,c2)) over MUL(v, c3)
2018-07-10 07:58:33 +00:00
vec_shift7.ll
[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT
2018-07-17 09:45:35 +00:00
vec_shift.ll
…
vec_shuf-insert.ll
…
vec_split.ll
…
vec_ss_load_fold.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
vec_trunc_sext.ll
…
vec_udiv_to_shift.ll
…
vec_uint_to_fp-fastmath.ll
…
vec_uint_to_fp.ll
…
vec_unsafe-fp-math.ll
…
vec_zero_cse.ll
…
vec_zero-2.ll
…
vec_zero.ll
…
vec-copysign-avx512.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vec-copysign.ll
…
vec-loadsingles-alignment.ll
…
vec-trunc-store.ll
…
vector-bitreverse.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vector-blend.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
vector-compare-all_of.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vector-compare-any_of.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vector-compare-combines.ll
…
vector-compare-results.ll
[SelectionDAG][ARM][X86] Teach PromoteIntRes_SETCC to do a better job picking the result type for the setcc.
2018-03-15 23:04:11 +00:00
vector-compare-simplify.ll
[SelectionDAG] Support some SimplifySetCC cases for comparing against vector splats of constants.
2018-03-01 22:15:39 +00:00
vector-constrained-fp-intrinsics.ll
[FPEnv] Expand constrained FP POWI
2018-06-15 20:57:55 +00:00
vector-extend-inreg.ll
[X86] Use 128-bit ops for 256-bit vzmovl patterns.
2018-07-15 18:51:07 +00:00
vector-gep.ll
…
vector-half-conversions.ll
[x86] NFC. Reautogenerate test/CodeGen/X86/vector-half-conversions.ll
2018-06-01 13:51:53 +00:00
vector-idiv-sdiv-128.ll
[X86] Remove sse41 specific code from lowering v16i8 multiply
2018-03-19 17:31:41 +00:00
vector-idiv-sdiv-256.ll
[X86] Remove sse41 specific code from lowering v16i8 multiply
2018-03-19 17:31:41 +00:00
vector-idiv-sdiv-512.ll
[X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads.
2018-01-18 07:44:06 +00:00
vector-idiv-udiv-128.ll
[X86] Remove sse41 specific code from lowering v16i8 multiply
2018-03-19 17:31:41 +00:00
vector-idiv-udiv-256.ll
[X86] Remove sse41 specific code from lowering v16i8 multiply
2018-03-19 17:31:41 +00:00
vector-idiv-udiv-512.ll
[X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads.
2018-01-18 07:44:06 +00:00
vector-idiv.ll
[X86] Change X86::PMULDQ/PMULUDQ opcodes to take vXi64 type as input instead of vXi32.
2018-03-08 08:02:52 +00:00
vector-interleave.ll
…
vector-intrinsics.ll
…
vector-lzcnt-128.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vector-lzcnt-256.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vector-lzcnt-512.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
vector-merge-store-fp-constants.ll
…
vector-mul.ll
Fix line endings. NFCI.
2018-07-09 20:52:07 +00:00
vector-narrow-binop.ll
…
vector-pcmp.ll
…
vector-popcnt-128.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vector-popcnt-256.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vector-popcnt-512.ll
…
vector-reduce-add.ll
[X86][SSE] Use SplitOpsAndApply to improve HADD/HSUB lowering
2018-07-20 16:20:45 +00:00
vector-reduce-and.ll
[X86][SSE] Add integer and/or/xor vector.reduce tests
2018-04-05 17:29:51 +00:00
vector-reduce-fadd-fast.ll
[X86][SSE] Add floating point add/mul fast-math vector.reduce tests
2018-04-05 21:01:21 +00:00
vector-reduce-fadd.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vector-reduce-fmax-nnan.ll
[X86][SSE] Add floating point min/max vector.reduce tests
2018-04-05 20:54:55 +00:00
vector-reduce-fmax.ll
[X86][SSE] Add floating point min/max vector.reduce tests
2018-04-05 20:54:55 +00:00
vector-reduce-fmin-nnan.ll
[X86][SSE] Add floating point min/max vector.reduce tests
2018-04-05 20:54:55 +00:00
vector-reduce-fmin.ll
[X86][SSE] Add floating point min/max vector.reduce tests
2018-04-05 20:54:55 +00:00
vector-reduce-fmul-fast.ll
[X86][SSE] Add floating point add/mul fast-math vector.reduce tests
2018-04-05 21:01:21 +00:00
vector-reduce-fmul.ll
[DAG] fold FP binops with undef operands to NaN
2018-05-21 23:54:19 +00:00
vector-reduce-mul.ll
[X86][SSE] Add integer add/mul vector.reduce tests
2018-04-05 17:37:35 +00:00
vector-reduce-or.ll
[X86][SSE] Add integer and/or/xor vector.reduce tests
2018-04-05 17:29:51 +00:00
vector-reduce-smax.ll
[X86][SSE] Add integer min/max vector.reduce tests
2018-04-05 17:25:40 +00:00
vector-reduce-smin.ll
[X86][SSE] Add integer min/max vector.reduce tests
2018-04-05 17:25:40 +00:00
vector-reduce-umax.ll
[X86][SSE] Add integer min/max vector.reduce tests
2018-04-05 17:25:40 +00:00
vector-reduce-umin.ll
[X86][SSE] Add integer min/max vector.reduce tests
2018-04-05 17:25:40 +00:00
vector-reduce-xor.ll
[X86][SSE] Add integer and/or/xor vector.reduce tests
2018-04-05 17:29:51 +00:00
vector-rem.ll
…
vector-rotate-128.ll
[X86][SSE] Support v16i8/v32i8 vector rotations
2018-06-29 09:36:39 +00:00
vector-rotate-256.ll
[X86][SSE] Support v16i8/v32i8 vector rotations
2018-06-29 09:36:39 +00:00
vector-rotate-512.ll
[X86][SSE] Support v16i8/v32i8 vector rotations
2018-06-29 09:36:39 +00:00
vector-sext.ll
[DAGCombiner] Change the SDLoc on split extloads (2/N)
2018-05-01 19:29:15 +00:00
vector-shift-ashr-128.ll
[X86] Remove isel patterns for MOVSS/MOVSD ISD opcodes with integer types.
2018-07-20 17:57:53 +00:00
vector-shift-ashr-256.ll
[X86][XOP] Fix SUB constant folding for VPSHA/VPSHL shift lowering
2018-07-20 16:55:18 +00:00
vector-shift-ashr-512.ll
[X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads.
2018-01-18 07:44:06 +00:00
vector-shift-lshr-128.ll
[X86] Remove isel patterns for MOVSS/MOVSD ISD opcodes with integer types.
2018-07-20 17:57:53 +00:00
vector-shift-lshr-256.ll
[X86][XOP] Fix SUB constant folding for VPSHA/VPSHL shift lowering
2018-07-20 16:55:18 +00:00
vector-shift-lshr-512.ll
[X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads.
2018-01-18 07:44:06 +00:00
vector-shift-shl-128.ll
Fix line endings. NFCI.
2018-07-09 20:52:07 +00:00
vector-shift-shl-256.ll
Fix line endings. NFCI.
2018-07-09 20:52:07 +00:00
vector-shift-shl-512.ll
…
vector-shuffle-128-v2.ll
[X86] Enable commuting of VUNPCKHPD to VMOVLHPS to enable load folding by using VMOVLPS with a modified address.
2018-07-18 07:31:32 +00:00
vector-shuffle-128-v4.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
vector-shuffle-128-v8.ll
[X86] Remove isel patterns for MOVSS/MOVSD ISD opcodes with integer types.
2018-07-20 17:57:53 +00:00
vector-shuffle-128-v16.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vector-shuffle-256-v4.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vector-shuffle-256-v8.ll
[X86] Fix a subtle bug in the custom execution domain fixing for blends.
2018-07-14 06:30:30 +00:00
vector-shuffle-256-v16.ll
[TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts
2018-03-06 22:32:01 +00:00
vector-shuffle-256-v32.ll
[X86][SSE] Utilize ZeroableElements for canWidenShuffleElements
2018-07-12 13:29:41 +00:00
vector-shuffle-512-v8.ll
[X86] Use 128-bit blends instead vmovss/vmovsd for 512-bit vzmovl patterns to match AVX.
2018-07-15 18:51:08 +00:00
vector-shuffle-512-v16.ll
[X86] Use 128-bit blends instead vmovss/vmovsd for 512-bit vzmovl patterns to match AVX.
2018-07-15 18:51:08 +00:00
vector-shuffle-512-v32.ll
…
vector-shuffle-512-v64.ll
…
vector-shuffle-avx512.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
vector-shuffle-combining-avx2.ll
[X86] Use 128-bit ops for 256-bit vzmovl patterns.
2018-07-15 18:51:07 +00:00
vector-shuffle-combining-avx512bw.ll
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade.
2018-05-29 05:22:05 +00:00
vector-shuffle-combining-avx512bwvl.ll
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade.
2018-05-29 05:22:05 +00:00
vector-shuffle-combining-avx512vbmi.ll
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade.
2018-05-29 05:22:05 +00:00
vector-shuffle-combining-avx.ll
[X86] Teach shuffle lowering to recognize 128/256 bit insertions into a zero vector.
2018-02-09 05:54:34 +00:00
vector-shuffle-combining-sse4a.ll
…
vector-shuffle-combining-sse41.ll
…
vector-shuffle-combining-ssse3.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
vector-shuffle-combining-xop.ll
[X86][SSE] Simplify demanded elements from BROADCAST shuffle source.
2018-01-27 19:48:13 +00:00
vector-shuffle-combining.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
vector-shuffle-masked.ll
[X86] Add isel patterns for selecting masked SUBV_BROADCAST with bitcasts. Remove combineBitcastForMaskedOp.
2018-02-05 08:37:37 +00:00
vector-shuffle-mmx.ll
[X86][MMX] Improve handling of 64-bit MMX constants
2018-03-01 22:22:31 +00:00
vector-shuffle-sse1.ll
[X86] Remove the vector alignment requirement from the patterns added in r337320.
2018-07-17 23:26:20 +00:00
vector-shuffle-sse4a.ll
…
vector-shuffle-sse41.ll
…
vector-shuffle-v1.ll
[X86] Use vpmovq2m/vpmovd2m for truncate to vXi1 when possible.
2018-02-19 22:07:31 +00:00
vector-shuffle-v48.ll
…
vector-shuffle-variable-128.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
vector-shuffle-variable-256.ll
[X86] Remove some composite MOVSS/MOVSD isel patterns.
2018-07-11 04:51:40 +00:00
vector-sqrt.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
vector-trunc-math.ll
[X86][SSE] Simplify combineVectorTruncationWithPACKUS to reduce code duplication
2018-06-08 13:59:11 +00:00
vector-trunc-packus.ll
[X86][SSE] Simplify combineVectorTruncationWithPACKUS to reduce code duplication
2018-06-08 13:59:11 +00:00
vector-trunc-ssat.ll
[X86][SSE] Simplify combineVectorTruncationWithPACKUS to reduce code duplication
2018-06-08 13:59:11 +00:00
vector-trunc-usat.ll
[X86][SSE] Simplify combineVectorTruncationWithPACKUS to reduce code duplication
2018-06-08 13:59:11 +00:00
vector-trunc.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vector-truncate-combine.ll
…
vector-tzcnt-128.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vector-tzcnt-256.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vector-tzcnt-512.ll
…
vector-unsigned-cmp.ll
…
vector-variable-idx2.ll
…
vector-variable-idx.ll
…
vector-zext.ll
[X86] Fix a subtle bug in the custom execution domain fixing for blends.
2018-07-14 06:30:30 +00:00
vector-zmov.ll
…
vector.ll
…
vectorcall.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
verifier-generic-extend-truncate.mir
[MachineVerifier][GlobalISel] Verifying generic extends and truncates
2018-05-08 02:48:15 +00:00
verifier-generic-types-1.mir
Follow Up on [MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visitMachineInstrBefore
2018-05-07 23:14:00 +00:00
verifier-generic-types-2.mir
[MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all vregs
2018-05-07 22:31:47 +00:00
verifier-phi-fail0.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
verifier-phi.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
version_directive.ll
…
vfcmp.ll
…
viabs.ll
…
virtual-registers-cleared-in-machine-functions-liveins.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
visibility2.ll
…
visibility.ll
…
vmaskmov-offset.ll
[SelectionDAG][X86] Fix incorrect offset generated for VMASKMOV
2018-02-14 15:55:24 +00:00
vmovq.ll
…
volatile.ll
…
vortex-bug.ll
…
vpshufbitqbm-intrinsics.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vsel-cmp-load.ll
[x86] eliminate even more sign-bit tests with vector select
2018-06-13 12:28:32 +00:00
vselect-2.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
vselect-avx.ll
[X86] Change X86::PMULDQ/PMULUDQ opcodes to take vXi64 type as input instead of vXi32.
2018-03-08 08:02:52 +00:00
vselect-constants.ll
…
vselect-minmax.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
vselect-packss.ll
[X86][SSE] truncateVectorWithPACK - Use src type instead of dst to select between PACK*SDW/PACK*SWB
2018-02-14 18:23:58 +00:00
vselect-pcmp.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vselect-zero.ll
…
vselect.ll
[X86] Correct SHRUNKBLEND creation to work correctly when there are multiple uses of the condition.
2018-02-20 17:58:17 +00:00
vshift_scalar.ll
…
vshift_split2.ll
…
vshift_split.ll
…
vshift-1.ll
…
vshift-2.ll
…
vshift-3.ll
…
vshift-4.ll
…
vshift-5.ll
…
vshift-6.ll
…
vsplit-and.ll
…
vzero-excess.ll
…
waitpkg-intrinsics.ll
[X86] WaitPKG instructions
2018-04-20 18:42:47 +00:00
warn-stack.ll
…
wbinvd-intrinsic.ll
[X86] Introduce LLVM wbinvd intrinsic
2018-04-12 18:38:18 +00:00
wbnoinvd-intrinsic.ll
[X86] Describe wbnoinvd instruction
2018-04-11 20:01:57 +00:00
weak_def_can_be_hidden.ll
…
weak-undef.ll
…
weak.ll
…
webkit-jscc.ll
…
wide-fma-contraction.ll
…
wide-integer-cmp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
wide-integer-fold.ll
…
widen_arith-1.ll
…
widen_arith-2.ll
[X86][SSE] Consistently prefer lowering to PACKUS over PACKSS
2018-06-08 10:29:00 +00:00
widen_arith-3.ll
…
widen_arith-4.ll
[X86][SSE] Prefer BLEND(SHL(v,c1),SHL(v,c2)) over MUL(v, c3)
2018-07-10 07:58:33 +00:00
widen_arith-5.ll
[DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N)
2018-05-11 18:40:08 +00:00
widen_arith-6.ll
…
widen_bitops-0.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
widen_bitops-1.ll
…
widen_cast-1.ll
…
widen_cast-2.ll
…
widen_cast-3.ll
…
widen_cast-4.ll
…
widen_cast-5.ll
…
widen_cast-6.ll
…
widen_compare-1.ll
…
widen_conv-1.ll
[TargetLowering] SimplifyDemandedVectorElts - pass demanded elts through ADD/SUB ops
2018-02-24 20:59:14 +00:00
widen_conv-2.ll
…
widen_conv-3.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
widen_conv-4.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
widen_conversions.ll
…
widen_extract-1.ll
…
widen_load-0.ll
…
widen_load-1.ll
…
widen_load-2.ll
[X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding (Reapplied)
2018-01-22 12:05:17 +00:00
widen_load-3.ll
…
widen_shuffle-1.ll
…
WidenArith.ll
…
widened-broadcast.ll
[X86][SSE] Simplify demanded elements from BROADCAST shuffle source.
2018-01-27 19:48:13 +00:00
win32_sret.ll
[FastISel] Sink local value materializations to first use
2018-03-14 21:54:21 +00:00
win32-bool.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
win32-eh-available-externally.ll
…
win32-eh-states.ll
…
win32-eh.ll
…
win32-pic-jumptable.ll
…
win32-preemption.ll
…
win32-seh-catchpad-realign.ll
…
win32-seh-catchpad.ll
…
win32-seh-nested-finally.ll
…
win32-spill-xmm.ll
…
win32-ssp.ll
[X86] Don't use the MSVC stack protector names on mingw
2018-03-20 20:37:51 +00:00
win64_alloca_dynalloca.ll
…
win64_call_epi.ll
…
win64_eh_leaf2.ll
…
win64_eh_leaf.ll
…
win64_eh.ll
…
win64_frame.ll
[x86] Switch EFLAGS copy lowering to use reg-reg form of testing for
2018-04-18 15:52:50 +00:00
win64_nonvol.ll
…
win64_params.ll
…
win64_sibcall.ll
…
win64_vararg.ll
…
win64-bool.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
win64-jumptable.ll
…
win64-long-double.ll
[X86] Properly implement the calling convention for f80 for mingw/x86_64
2018-03-20 06:19:38 +00:00
win64-nosse-csrs.ll
…
win_chkstk.ll
…
win_coreclr_chkstk.ll
…
win_cst_pool.ll
[COFF] Fix constant sharing regression for MinGW
2018-06-28 20:28:29 +00:00
win-alloca-expander.ll
…
win-catchpad-csrs.ll
…
win-catchpad-nested-cxx.ll
…
win-catchpad-nested.ll
…
win-catchpad-varargs.ll
…
win-catchpad.ll
…
win-cleanuppad.ll
…
win-funclet-cfi.ll
…
win-mixed-ehpersonality.ll
…
win-smallparams.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
windows-itanium-alloca.ll
…
wineh-coreclr.ll
…
wineh-exceptionpointer.ll
…
wineh-no-ehpads.ll
…
x32-cet-intrinsics.ll
[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
2018-05-18 11:58:25 +00:00
x32-function_pointer-1.ll
…
x32-function_pointer-2.ll
…
x32-function_pointer-3.ll
…
x32-indirectbr.ll
…
x32-landingpad.ll
…
x32-lea-1.ll
…
x32-movtopush64.ll
…
x32-va_start.ll
…
x64-cet-intrinsics.ll
[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
2018-05-18 11:58:25 +00:00
x86_64-mul-by-const.ll
…
x86-16.ll
…
x86-32-intrcc.ll
…
x86-32-vector-calling-conv.ll
…
x86-64-and-mask.ll
…
x86-64-arg.ll
…
x86-64-asm.ll
…
x86-64-baseptr.ll
[X86][x32] Save callee-save register used as base pointer for x32 ABI
2018-03-02 17:46:39 +00:00
x86-64-bittest-logic.ll
[X86] Add the test cases that were supposed to go with r325287.
2018-02-16 00:39:05 +00:00
x86-64-call.ll
…
x86-64-disp.ll
…
x86-64-double-precision-shift-left.ll
[X86] Regenerate double shift tests
2018-01-13 16:55:28 +00:00
x86-64-double-precision-shift-right.ll
[X86] Regenerate double shift tests
2018-01-13 16:55:28 +00:00
x86-64-double-shifts-Oz-Os-O2.ll
[X86] Regenerate double shift tests
2018-01-13 16:55:28 +00:00
x86-64-double-shifts-var.ll
…
x86-64-extend-shift.ll
…
x86-64-flags-intrinsics.ll
…
x86-64-gv-offset.ll
…
x86-64-intrcc-nosse.ll
…
x86-64-intrcc.ll
…
x86-64-jumps.ll
…
x86-64-mem.ll
…
x86-64-ms_abi-vararg.ll
…
x86-64-pic-1.ll
…
x86-64-pic-2.ll
…
x86-64-pic-3.ll
…
x86-64-pic-4.ll
…
x86-64-pic-5.ll
…
x86-64-pic-6.ll
…
x86-64-pic-7.ll
…
x86-64-pic-8.ll
…
x86-64-pic-9.ll
…
x86-64-pic-10.ll
…
x86-64-pic-11.ll
…
x86-64-pic-12.ll
…
x86-64-pic.ll
…
x86-64-plt-relative-reloc.ll
…
x86-64-psub.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
x86-64-ptr-arg-simple.ll
…
x86-64-ret0.ll
…
x86-64-shortint.ll
…
x86-64-sret-return-2.ll
…
x86-64-sret-return.ll
…
x86-64-stack-and-frame-ptr.ll
…
x86-64-static-relo-movl.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
x86-64-tls-1.ll
…
x86-64-varargs.ll
…
x86-big-ret.ll
…
x86-cmov-converter.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
x86-flags-intrinsics.ll
…
x86-fold-pshufb.ll
…
x86-framelowering-trap.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
x86-inline-asm-validation.ll
…
x86-interleaved-access.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
x86-interleaved-check.ll
…
x86-interrupt_cc.ll
[llvm-mc] - Produce R_X86_64_PLT32 for "call/jmp foo".
2018-02-20 10:17:57 +00:00
x86-interrupt_cld.ll
…
x86-interrupt_vzeroupper.ll
…
x86-mixed-alignment-dagcombine.ll
…
x86-no_caller_saved_registers-preserve.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
x86-no_caller_saved_registers.ll
…
x86-plt-relative-reloc.ll
…
x86-repmov-copy-eflags.ll
[x86] Switch EFLAGS copy lowering to use reg-reg form of testing for
2018-04-18 15:52:50 +00:00
x86-sanitizer-shrink-wrapping.ll
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x86-setcc-int-to-fp-combine.ll
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x86-shifts.ll
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x86-shrink-wrap-unwind.ll
[ShrinkWrap] Take into account landing pad
2018-03-20 02:44:40 +00:00
x86-shrink-wrapping.ll
[ShrinkWrap] Add optimization remarks to the shrink-wrapping pass
2018-06-05 00:27:24 +00:00
x86-store-gv-addr.ll
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x86-upgrade-avx2-vbroadcast.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
x86-upgrade-avx-vbroadcast.ll
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x86-win64-shrink-wrapping.ll
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x87-schedule.ll
[CodeGen] assume max/default throughput for unspecified instructions
2018-06-05 23:34:45 +00:00
x87.ll
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xaluo.ll
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xchg-nofold.ll
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xmm-r64.ll
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xmulo.ll
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xop-ifma.ll
[X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of lowering.
2018-04-07 19:09:52 +00:00
xop-intrinsics-fast-isel.ll
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xop-intrinsics-x86_64-upgrade.ll
…
xop-intrinsics-x86_64.ll
…
xop-mask-comments.ll
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xop-pcmov.ll
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xop-schedule.ll
[X86] Split WriteVecALU/WriteVecLogic/WriteShuffle/WriteVarShuffle/WritePSADBW/WritePHAdd scheduler classes
2018-05-10 17:06:09 +00:00
xor-combine-debugloc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
xor-icmp.ll
[X86] Only reorder srl/and on last DAG combiner run
2018-02-16 18:51:09 +00:00
xor-select-i1-combine.ll
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xor.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
xray-attribute-instrumentation.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-custom-log.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-empty-firstmbb.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
xray-empty-function.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
xray-log-args.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-loop-detection.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-multiplerets-in-blocks.mir
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-section-group.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-selective-instrumentation-miss.ll
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xray-selective-instrumentation.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-tail-call-sled.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-typed-event-log.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xtest.ll
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zero-remat.ll
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zext-demanded.ll
[X86] Teach X86TargetLowering::targetShrinkDemandedConstant to set non-demanded bits if it helps created an and mask that can be matched as a zero extend.
2018-03-14 16:55:15 +00:00
zext-extract_subreg.ll
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zext-fold.ll
[x86] shrink 'and' immediate values by setting the high bits (PR35907)
2018-01-19 16:37:25 +00:00
zext-inreg-0.ll
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zext-inreg-1.ll
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zext-logicop-shift-load.ll
[CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions
2018-06-05 21:03:52 +00:00
zext-sext.ll
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zext-shl.ll
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zext-trunc.ll
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zlib-longest-match.ll
…