mirror of
https://github.com/RPCS3/llvm.git
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bb8c53976b
Summary: Add support for atomic store instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48839 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336145 91177308-0d34-0410-b5e6-96231b3b80d8
353 lines
18 KiB
TableGen
353 lines
18 KiB
TableGen
// WebAssemblyInstrAtomics.td-WebAssembly Atomic codegen support-*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// WebAssembly Atomic operand code-gen constructs.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Atomic loads
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//===----------------------------------------------------------------------===//
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let Defs = [ARGUMENTS] in {
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defm ATOMIC_LOAD_I32 : WebAssemblyLoad<I32, "i32.atomic.load", 0xfe10>;
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defm ATOMIC_LOAD_I64 : WebAssemblyLoad<I64, "i64.atomic.load", 0xfe11>;
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} // Defs = [ARGUMENTS]
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// Select loads with no constant offset.
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let Predicates = [HasAtomics] in {
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def : LoadPatNoOffset<i32, atomic_load_32, ATOMIC_LOAD_I32>;
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def : LoadPatNoOffset<i64, atomic_load_64, ATOMIC_LOAD_I64>;
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// Select loads with a constant offset.
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// Pattern with address + immediate offset
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def : LoadPatImmOff<i32, atomic_load_32, regPlusImm, ATOMIC_LOAD_I32>;
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def : LoadPatImmOff<i64, atomic_load_64, regPlusImm, ATOMIC_LOAD_I64>;
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def : LoadPatImmOff<i32, atomic_load_32, or_is_add, ATOMIC_LOAD_I32>;
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def : LoadPatImmOff<i64, atomic_load_64, or_is_add, ATOMIC_LOAD_I64>;
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def : LoadPatGlobalAddr<i32, atomic_load_32, ATOMIC_LOAD_I32>;
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def : LoadPatGlobalAddr<i64, atomic_load_64, ATOMIC_LOAD_I64>;
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def : LoadPatExternalSym<i32, atomic_load_32, ATOMIC_LOAD_I32>;
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def : LoadPatExternalSym<i64, atomic_load_64, ATOMIC_LOAD_I64>;
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// Select loads with just a constant offset.
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def : LoadPatOffsetOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>;
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def : LoadPatOffsetOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
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def : LoadPatGlobalAddrOffOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>;
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def : LoadPatGlobalAddrOffOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
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def : LoadPatExternSymOffOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>;
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def : LoadPatExternSymOffOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
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} // Predicates = [HasAtomics]
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// Extending loads. Note that there are only zero-extending atomic loads, no
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// sign-extending loads.
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let Defs = [ARGUMENTS] in {
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defm ATOMIC_LOAD8_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load8_u", 0xfe12>;
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defm ATOMIC_LOAD16_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load16_u", 0xfe13>;
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defm ATOMIC_LOAD8_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load8_u", 0xfe14>;
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defm ATOMIC_LOAD16_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load16_u", 0xfe15>;
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defm ATOMIC_LOAD32_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load32_u", 0xfe16>;
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} // Defs = [ARGUMENTS]
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// Fragments for exending loads. These are different from regular loads because
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// the SDNodes are derived from AtomicSDNode rather than LoadSDNode and
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// therefore don't have the extension type field. So instead of matching that,
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// we match the patterns that the type legalizer expands them to.
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// We directly match zext patterns and select the zext atomic loads.
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// i32 (zext (i8 (atomic_load_8))) gets legalized to
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// i32 (and (i32 (atomic_load_8)), 255)
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// These can be selected to a single zero-extending atomic load instruction.
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def zext_aload_8 : PatFrag<(ops node:$addr),
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(and (i32 (atomic_load_8 node:$addr)), 255)>;
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def zext_aload_16 : PatFrag<(ops node:$addr),
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(and (i32 (atomic_load_16 node:$addr)), 65535)>;
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// Unlike regular loads, extension to i64 is handled differently than i32.
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// i64 (zext (i8 (atomic_load_8))) gets legalized to
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// i64 (and (i64 (anyext (i32 (atomic_load_8)))), 255)
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def zext_aload_8_64 :
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PatFrag<(ops node:$addr),
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(and (i64 (anyext (i32 (atomic_load_8 node:$addr)))), 255)>;
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def zext_aload_16_64 :
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PatFrag<(ops node:$addr),
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(and (i64 (anyext (i32 (atomic_load_16 node:$addr)))), 65535)>;
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def zext_aload_32_64 :
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PatFrag<(ops node:$addr),
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(zext (i32 (atomic_load node:$addr)))>;
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// We don't have single sext atomic load instructions. So for sext loads, we
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// match bare subword loads (for 32-bit results) and anyext loads (for 64-bit
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// results) and select a zext load; the next instruction will be sext_inreg
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// which is selected by itself.
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def anyext_aload_8_64 :
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PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_8 node:$addr)))>;
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def anyext_aload_16_64 :
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PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_16 node:$addr)))>;
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let Predicates = [HasAtomics] in {
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// Select zero-extending loads with no constant offset.
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def : LoadPatNoOffset<i32, zext_aload_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatNoOffset<i32, zext_aload_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatNoOffset<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatNoOffset<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatNoOffset<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
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// Select sign-extending loads with no constant offset
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def : LoadPatNoOffset<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatNoOffset<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatNoOffset<i64, anyext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatNoOffset<i64, anyext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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// 32->64 sext load gets selected as i32.atomic.load, i64.extend_s/i64
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// Zero-extending loads with constant offset
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def : LoadPatImmOff<i32, zext_aload_8, regPlusImm, ATOMIC_LOAD8_U_I32>;
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def : LoadPatImmOff<i32, zext_aload_16, regPlusImm, ATOMIC_LOAD16_U_I32>;
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def : LoadPatImmOff<i32, zext_aload_8, or_is_add, ATOMIC_LOAD8_U_I32>;
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def : LoadPatImmOff<i32, zext_aload_16, or_is_add, ATOMIC_LOAD16_U_I32>;
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def : LoadPatImmOff<i64, zext_aload_8_64, regPlusImm, ATOMIC_LOAD8_U_I64>;
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def : LoadPatImmOff<i64, zext_aload_16_64, regPlusImm, ATOMIC_LOAD16_U_I64>;
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def : LoadPatImmOff<i64, zext_aload_32_64, regPlusImm, ATOMIC_LOAD32_U_I64>;
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def : LoadPatImmOff<i64, zext_aload_8_64, or_is_add, ATOMIC_LOAD8_U_I64>;
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def : LoadPatImmOff<i64, zext_aload_16_64, or_is_add, ATOMIC_LOAD16_U_I64>;
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def : LoadPatImmOff<i64, zext_aload_32_64, or_is_add, ATOMIC_LOAD32_U_I64>;
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// Sign-extending loads with constant offset
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def : LoadPatImmOff<i32, atomic_load_8, regPlusImm, ATOMIC_LOAD8_U_I32>;
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def : LoadPatImmOff<i32, atomic_load_16, regPlusImm, ATOMIC_LOAD16_U_I32>;
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def : LoadPatImmOff<i32, atomic_load_8, or_is_add, ATOMIC_LOAD8_U_I32>;
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def : LoadPatImmOff<i32, atomic_load_16, or_is_add, ATOMIC_LOAD16_U_I32>;
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def : LoadPatImmOff<i64, anyext_aload_8_64, regPlusImm, ATOMIC_LOAD8_U_I64>;
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def : LoadPatImmOff<i64, anyext_aload_16_64, regPlusImm, ATOMIC_LOAD16_U_I64>;
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def : LoadPatImmOff<i64, anyext_aload_8_64, or_is_add, ATOMIC_LOAD8_U_I64>;
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def : LoadPatImmOff<i64, anyext_aload_16_64, or_is_add, ATOMIC_LOAD16_U_I64>;
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// No 32->64 patterns, just use i32.atomic.load and i64.extend_s/i64
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def : LoadPatGlobalAddr<i32, zext_aload_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatGlobalAddr<i32, zext_aload_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatGlobalAddr<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatGlobalAddr<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatGlobalAddr<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
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def : LoadPatGlobalAddr<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatGlobalAddr<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatGlobalAddr<i64, anyext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatGlobalAddr<i64, anyext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatExternalSym<i32, zext_aload_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatExternalSym<i32, zext_aload_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatExternalSym<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatExternalSym<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatExternalSym<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
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def : LoadPatExternalSym<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatExternalSym<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatExternalSym<i64, anyext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatExternalSym<i64, anyext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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// Extending loads with just a constant offset
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def : LoadPatOffsetOnly<i32, zext_aload_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatOffsetOnly<i32, zext_aload_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatOffsetOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatOffsetOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatOffsetOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
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def : LoadPatOffsetOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatOffsetOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatOffsetOnly<i64, anyext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatOffsetOnly<i64, anyext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatGlobalAddrOffOnly<i32, zext_aload_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatGlobalAddrOffOnly<i32, zext_aload_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatGlobalAddrOffOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatGlobalAddrOffOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatGlobalAddrOffOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
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def : LoadPatGlobalAddrOffOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatGlobalAddrOffOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatGlobalAddrOffOnly<i64, anyext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatGlobalAddrOffOnly<i64, anyext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatExternSymOffOnly<i32, zext_aload_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatExternSymOffOnly<i32, zext_aload_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatExternSymOffOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatExternSymOffOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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def : LoadPatExternSymOffOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
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def : LoadPatExternSymOffOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
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def : LoadPatExternSymOffOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
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def : LoadPatExternSymOffOnly<i64, anyext_aload_8_64, ATOMIC_LOAD8_U_I64>;
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def : LoadPatExternSymOffOnly<i64, anyext_aload_16_64, ATOMIC_LOAD16_U_I64>;
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} // Predicates = [HasAtomics]
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//===----------------------------------------------------------------------===//
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// Atomic stores
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//===----------------------------------------------------------------------===//
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let Defs = [ARGUMENTS] in {
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defm ATOMIC_STORE_I32 : WebAssemblyStore<I32, "i32.atomic.store", 0xfe17>;
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defm ATOMIC_STORE_I64 : WebAssemblyStore<I64, "i64.atomic.store", 0xfe18>;
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} // Defs = [ARGUMENTS]
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// We need an 'atomic' version of store patterns because store and atomic_store
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// nodes have different operand orders:
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// store: (store $val, $ptr)
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// atomic_store: (store $ptr, $val)
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let Predicates = [HasAtomics] in {
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// Select stores with no constant offset.
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class AStorePatNoOffset<ValueType ty, PatFrag node, NI inst> :
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Pat<(node I32:$addr, ty:$val), (inst 0, 0, $addr, $val)>;
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def : AStorePatNoOffset<i32, atomic_store_32, ATOMIC_STORE_I32>;
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def : AStorePatNoOffset<i64, atomic_store_64, ATOMIC_STORE_I64>;
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// Select stores with a constant offset.
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// Pattern with address + immediate offset
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class AStorePatImmOff<ValueType ty, PatFrag storekind, PatFrag operand,
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NI inst> :
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Pat<(storekind (operand I32:$addr, imm:$off), ty:$val),
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(inst 0, imm:$off, $addr, ty:$val)>;
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def : AStorePatImmOff<i32, atomic_store_32, regPlusImm, ATOMIC_STORE_I32>;
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def : AStorePatImmOff<i64, atomic_store_64, regPlusImm, ATOMIC_STORE_I64>;
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def : AStorePatImmOff<i32, atomic_store_32, or_is_add, ATOMIC_STORE_I32>;
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def : AStorePatImmOff<i64, atomic_store_64, or_is_add, ATOMIC_STORE_I64>;
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class AStorePatGlobalAddr<ValueType ty, PatFrag storekind, NI inst> :
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Pat<(storekind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
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ty:$val),
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(inst 0, tglobaladdr:$off, I32:$addr, ty:$val)>;
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def : AStorePatGlobalAddr<i32, atomic_store_32, ATOMIC_STORE_I32>;
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def : AStorePatGlobalAddr<i64, atomic_store_64, ATOMIC_STORE_I64>;
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class AStorePatExternalSym<ValueType ty, PatFrag storekind, NI inst> :
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Pat<(storekind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)),
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ty:$val),
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(inst 0, texternalsym:$off, I32:$addr, ty:$val)>;
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def : AStorePatExternalSym<i32, atomic_store_32, ATOMIC_STORE_I32>;
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def : AStorePatExternalSym<i64, atomic_store_64, ATOMIC_STORE_I64>;
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// Select stores with just a constant offset.
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class AStorePatOffsetOnly<ValueType ty, PatFrag storekind, NI inst> :
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Pat<(storekind imm:$off, ty:$val),
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(inst 0, imm:$off, (CONST_I32 0), ty:$val)>;
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def : AStorePatOffsetOnly<i32, atomic_store_32, ATOMIC_STORE_I32>;
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def : AStorePatOffsetOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
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class AStorePatGlobalAddrOffOnly<ValueType ty, PatFrag storekind, NI inst> :
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Pat<(storekind (WebAssemblywrapper tglobaladdr:$off), ty:$val),
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(inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$val)>;
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def : AStorePatGlobalAddrOffOnly<i32, atomic_store_32, ATOMIC_STORE_I32>;
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def : AStorePatGlobalAddrOffOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
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class AStorePatExternSymOffOnly<ValueType ty, PatFrag storekind, NI inst> :
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Pat<(storekind (WebAssemblywrapper texternalsym:$off), ty:$val),
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(inst 0, texternalsym:$off, (CONST_I32 0), ty:$val)>;
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def : AStorePatExternSymOffOnly<i32, atomic_store_32, ATOMIC_STORE_I32>;
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def : AStorePatExternSymOffOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
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} // Predicates = [HasAtomics]
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// Truncating stores.
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let Defs = [ARGUMENTS] in {
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defm ATOMIC_STORE8_I32 : WebAssemblyStore<I32, "i32.atomic.store8", 0xfe19>;
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defm ATOMIC_STORE16_I32 : WebAssemblyStore<I32, "i32.atomic.store16", 0xfe1a>;
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defm ATOMIC_STORE8_I64 : WebAssemblyStore<I64, "i64.atomic.store8", 0xfe1b>;
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defm ATOMIC_STORE16_I64 : WebAssemblyStore<I64, "i64.atomic.store16", 0xfe1c>;
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defm ATOMIC_STORE32_I64 : WebAssemblyStore<I64, "i64.atomic.store32", 0xfe1d>;
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} // Defs = [ARGUMENTS]
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// Fragments for truncating stores.
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// We don't have single truncating atomic store instructions. For 32-bit
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// instructions, we just need to match bare atomic stores. On the other hand,
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// truncating stores from i64 values are once truncated to i32 first.
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class trunc_astore_64<PatFrag storekind> :
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PatFrag<(ops node:$addr, node:$val),
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(storekind node:$addr, (i32 (trunc (i64 node:$val))))>;
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def trunc_astore_8_64 : trunc_astore_64<atomic_store_8>;
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def trunc_astore_16_64 : trunc_astore_64<atomic_store_16>;
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def trunc_astore_32_64 : trunc_astore_64<atomic_store_32>;
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let Predicates = [HasAtomics] in {
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// Truncating stores with no constant offset
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def : AStorePatNoOffset<i32, atomic_store_8, ATOMIC_STORE8_I32>;
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def : AStorePatNoOffset<i32, atomic_store_16, ATOMIC_STORE16_I32>;
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def : AStorePatNoOffset<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
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def : AStorePatNoOffset<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
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def : AStorePatNoOffset<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
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// Truncating stores with a constant offset
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def : AStorePatImmOff<i32, atomic_store_8, regPlusImm, ATOMIC_STORE8_I32>;
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def : AStorePatImmOff<i32, atomic_store_16, regPlusImm, ATOMIC_STORE16_I32>;
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def : AStorePatImmOff<i64, trunc_astore_8_64, regPlusImm, ATOMIC_STORE8_I64>;
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def : AStorePatImmOff<i64, trunc_astore_16_64, regPlusImm, ATOMIC_STORE16_I64>;
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def : AStorePatImmOff<i64, trunc_astore_32_64, regPlusImm, ATOMIC_STORE32_I64>;
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def : AStorePatImmOff<i32, atomic_store_8, or_is_add, ATOMIC_STORE8_I32>;
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def : AStorePatImmOff<i32, atomic_store_16, or_is_add, ATOMIC_STORE16_I32>;
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def : AStorePatImmOff<i64, trunc_astore_8_64, or_is_add, ATOMIC_STORE8_I64>;
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def : AStorePatImmOff<i64, trunc_astore_16_64, or_is_add, ATOMIC_STORE16_I64>;
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def : AStorePatImmOff<i64, trunc_astore_32_64, or_is_add, ATOMIC_STORE32_I64>;
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def : AStorePatGlobalAddr<i32, atomic_store_8, ATOMIC_STORE8_I32>;
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def : AStorePatGlobalAddr<i32, atomic_store_16, ATOMIC_STORE16_I32>;
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def : AStorePatGlobalAddr<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
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def : AStorePatGlobalAddr<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
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def : AStorePatGlobalAddr<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
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def : AStorePatExternalSym<i32, atomic_store_8, ATOMIC_STORE8_I32>;
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def : AStorePatExternalSym<i32, atomic_store_16, ATOMIC_STORE16_I32>;
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def : AStorePatExternalSym<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
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def : AStorePatExternalSym<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
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def : AStorePatExternalSym<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
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// Truncating stores with just a constant offset
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def : AStorePatOffsetOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>;
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def : AStorePatOffsetOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>;
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def : AStorePatOffsetOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
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def : AStorePatOffsetOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
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def : AStorePatOffsetOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
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def : AStorePatGlobalAddrOffOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>;
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def : AStorePatGlobalAddrOffOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>;
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def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
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def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
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def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
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def : AStorePatExternSymOffOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>;
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def : AStorePatExternSymOffOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>;
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def : AStorePatExternSymOffOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
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def : AStorePatExternSymOffOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
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def : AStorePatExternSymOffOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
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} // Predicates = [HasAtomics]
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//===----------------------------------------------------------------------===//
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// Low-level exclusive operations
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//===----------------------------------------------------------------------===//
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// TODO: add exclusive operations here...
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// Load-exclusives.
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// Store-exclusives.
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// Store-release-exclusives.
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// And clear exclusive.
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