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Farhana Aleen 13f7859c20 [SLP] Recognize min/max pattern using instructions producing same values.

Summary: It is common to have the following min/max pattern during the intermediate stages of SLP since we only optimize at the end. This patch tries to catch such patterns and allow more vectorization.

         %1 = extractelement <2 x i32> %a, i32 0
         %2 = extractelement <2 x i32> %a, i32 1
         %cond = icmp sgt i32 %1, %2
         %3 = extractelement <2 x i32> %a, i32 0
         %4 = extractelement <2 x i32> %a, i32 1
         %select = select i1 %cond, i32 %3, i32 %4

Author: FarhanaAleen

Reviewed By: ABataev, RKSimon, spatel

Differential Revision: https://reviews.llvm.org/D47608

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336130 91177308-0d34-0410-b5e6-96231b3b80d8

2018-07-02 17:55:31 +00:00

AArch64

[SLPVectorizer] Relax alternate opcodes to accept any BinaryOperator pair

2018-06-22 14:04:06 +00:00

AMDGPU

[SLP] Recognize min/max pattern using instructions producing same values.

2018-07-02 17:55:31 +00:00

ARM

[SLPVectorizer] add test for PR13837; NFC

2018-01-23 22:04:17 +00:00

NVPTX

[NVPTX] Turn on Loop/SLP vectorization