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------------------------------------------------------------------------ r323155 | chandlerc | 2018-01-22 23:05:25 +0100 (Mon, 22 Jan 2018) | 133 lines Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre.. Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all shared libraries with LLD and pass `-z retpolineplt` (or use similar functionality from some other linker). We strongly recommend also using `-z now` as non-lazy binding allows the retpoline-mitigated PLT to be substantially smaller. When manually apply similar transformations to `-mretpoline` to the Linux kernel we observed very small performance hits to applications running typical workloads, and relatively minor hits (approximately 2%) even for extremely syscall-heavy applications. This is largely due to the small number of indirect branches that occur in performance sensitive paths of the kernel. When using these patches on statically linked applications, especially C++ applications, you should expect to see a much more dramatic performance hit. For microbenchmarks that are switch, indirect-, or virtual-call heavy we have seen overheads ranging from 10% to 50%. However, real-world workloads exhibit substantially lower performance impact. Notably, techniques such as PGO and ThinLTO dramatically reduce the impact of hot indirect calls (by speculatively promoting them to direct calls) and allow optimized search trees to be used to lower switches. If you need to deploy these techniques in C++ applications, we *strongly* recommend that you ensure all hot call targets are statically linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well tuned servers using all of these techniques saw 5% - 10% overhead from the use of retpoline. We will add detailed documentation covering these components in subsequent patches, but wanted to make the core functionality available as soon as possible. Happy for more code review, but we'd really like to get these patches landed and backported ASAP for obvious reasons. We're planning to backport this to both 6.0 and 5.0 release streams and get a 5.0 release with just this cherry picked ASAP for distros and vendors. This patch is the work of a number of people over the past month: Eric, Reid, Rui, and myself. I'm mailing it out as a single commit due to the time sensitive nature of landing this and the need to backport it. Huge thanks to everyone who helped out here, and everyone at Intel who helped out in discussions about how to craft this. Also, credit goes to Paul Turner (at Google, but not an LLVM contributor) for much of the underlying retpoline design. Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41723 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@324067 91177308-0d34-0410-b5e6-96231b3b80d8
426 lines
16 KiB
C++
426 lines
16 KiB
C++
//===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines interfaces to access the target independent code generation
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// passes provided by the LLVM backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_PASSES_H
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#define LLVM_CODEGEN_PASSES_H
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#include <functional>
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#include <string>
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namespace llvm {
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class FunctionPass;
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class MachineFunction;
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class MachineFunctionPass;
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class ModulePass;
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class Pass;
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class TargetMachine;
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class TargetRegisterClass;
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class raw_ostream;
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} // End llvm namespace
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/// List of target independent CodeGen pass IDs.
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namespace llvm {
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FunctionPass *createAtomicExpandPass();
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/// createUnreachableBlockEliminationPass - The LLVM code generator does not
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/// work well with unreachable basic blocks (what live ranges make sense for a
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/// block that cannot be reached?). As such, a code generator should either
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/// not instruction select unreachable blocks, or run this pass as its
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/// last LLVM modifying pass to clean up blocks that are not reachable from
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/// the entry block.
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FunctionPass *createUnreachableBlockEliminationPass();
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/// MachineFunctionPrinter pass - This pass prints out the machine function to
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/// the given stream as a debugging tool.
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MachineFunctionPass *
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createMachineFunctionPrinterPass(raw_ostream &OS,
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const std::string &Banner ="");
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/// MIRPrinting pass - this pass prints out the LLVM IR into the given stream
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/// using the MIR serialization format.
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MachineFunctionPass *createPrintMIRPass(raw_ostream &OS);
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/// This pass resets a MachineFunction when it has the FailedISel property
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/// as if it was just created.
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/// If EmitFallbackDiag is true, the pass will emit a
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/// DiagnosticInfoISelFallback for every MachineFunction it resets.
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/// If AbortOnFailedISel is true, abort compilation instead of resetting.
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MachineFunctionPass *createResetMachineFunctionPass(bool EmitFallbackDiag,
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bool AbortOnFailedISel);
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/// createCodeGenPreparePass - Transform the code to expose more pattern
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/// matching during instruction selection.
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FunctionPass *createCodeGenPreparePass();
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/// createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather
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/// and scatter intrinsics with scalar code when target doesn't support them.
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FunctionPass *createScalarizeMaskedMemIntrinPass();
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/// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
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/// load-linked/store-conditional loops.
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extern char &AtomicExpandID;
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/// MachineLoopInfo - This pass is a loop analysis pass.
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extern char &MachineLoopInfoID;
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/// MachineDominators - This pass is a machine dominators analysis pass.
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extern char &MachineDominatorsID;
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/// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
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extern char &MachineDominanceFrontierID;
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/// MachineRegionInfo - This pass computes SESE regions for machine functions.
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extern char &MachineRegionInfoPassID;
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/// EdgeBundles analysis - Bundle machine CFG edges.
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extern char &EdgeBundlesID;
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/// LiveVariables pass - This pass computes the set of blocks in which each
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/// variable is life and sets machine operand kill flags.
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extern char &LiveVariablesID;
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/// PHIElimination - This pass eliminates machine instruction PHI nodes
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/// by inserting copy instructions. This destroys SSA information, but is the
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/// desired input for some register allocators. This pass is "required" by
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/// these register allocator like this: AU.addRequiredID(PHIEliminationID);
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extern char &PHIEliminationID;
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/// LiveIntervals - This analysis keeps track of the live ranges of virtual
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/// and physical registers.
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extern char &LiveIntervalsID;
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/// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
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extern char &LiveStacksID;
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/// TwoAddressInstruction - This pass reduces two-address instructions to
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/// use two operands. This destroys SSA information but it is desired by
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/// register allocators.
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extern char &TwoAddressInstructionPassID;
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/// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
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extern char &ProcessImplicitDefsID;
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/// RegisterCoalescer - This pass merges live ranges to eliminate copies.
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extern char &RegisterCoalescerID;
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/// MachineScheduler - This pass schedules machine instructions.
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extern char &MachineSchedulerID;
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/// PostMachineScheduler - This pass schedules machine instructions postRA.
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extern char &PostMachineSchedulerID;
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/// SpillPlacement analysis. Suggest optimal placement of spill code between
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/// basic blocks.
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extern char &SpillPlacementID;
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/// ShrinkWrap pass. Look for the best place to insert save and restore
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// instruction and update the MachineFunctionInfo with that information.
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extern char &ShrinkWrapID;
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/// LiveRangeShrink pass. Move instruction close to its definition to shrink
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/// the definition's live range.
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extern char &LiveRangeShrinkID;
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/// Greedy register allocator.
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extern char &RAGreedyID;
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/// Basic register allocator.
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extern char &RABasicID;
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/// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
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/// assigned in VirtRegMap.
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extern char &VirtRegRewriterID;
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/// UnreachableMachineBlockElimination - This pass removes unreachable
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/// machine basic blocks.
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extern char &UnreachableMachineBlockElimID;
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/// DeadMachineInstructionElim - This pass removes dead machine instructions.
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extern char &DeadMachineInstructionElimID;
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/// This pass adds dead/undef flags after analyzing subregister lanes.
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extern char &DetectDeadLanesID;
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/// FastRegisterAllocation Pass - This pass register allocates as fast as
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/// possible. It is best suited for debug code where live ranges are short.
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///
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FunctionPass *createFastRegisterAllocator();
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/// BasicRegisterAllocation Pass - This pass implements a degenerate global
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/// register allocator using the basic regalloc framework.
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///
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FunctionPass *createBasicRegisterAllocator();
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/// Greedy register allocation pass - This pass implements a global register
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/// allocator for optimized builds.
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///
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FunctionPass *createGreedyRegisterAllocator();
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/// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
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/// Quadratic Prograaming (PBQP) based register allocator.
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///
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FunctionPass *createDefaultPBQPRegisterAllocator();
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/// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
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/// and eliminates abstract frame references.
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extern char &PrologEpilogCodeInserterID;
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MachineFunctionPass *createPrologEpilogInserterPass();
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/// ExpandPostRAPseudos - This pass expands pseudo instructions after
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/// register allocation.
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extern char &ExpandPostRAPseudosID;
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/// createPostRAHazardRecognizer - This pass runs the post-ra hazard
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/// recognizer.
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extern char &PostRAHazardRecognizerID;
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/// createPostRAScheduler - This pass performs post register allocation
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/// scheduling.
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extern char &PostRASchedulerID;
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/// BranchFolding - This pass performs machine code CFG based
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/// optimizations to delete branches to branches, eliminate branches to
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/// successor blocks (creating fall throughs), and eliminating branches over
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/// branches.
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extern char &BranchFolderPassID;
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/// BranchRelaxation - This pass replaces branches that need to jump further
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/// than is supported by a branch instruction.
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extern char &BranchRelaxationPassID;
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/// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
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extern char &MachineFunctionPrinterPassID;
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/// MIRPrintingPass - this pass prints out the LLVM IR using the MIR
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/// serialization format.
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extern char &MIRPrintingPassID;
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/// TailDuplicate - Duplicate blocks with unconditional branches
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/// into tails of their predecessors.
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extern char &TailDuplicateID;
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/// MachineTraceMetrics - This pass computes critical path and CPU resource
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/// usage in an ensemble of traces.
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extern char &MachineTraceMetricsID;
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/// EarlyIfConverter - This pass performs if-conversion on SSA form by
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/// inserting cmov instructions.
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extern char &EarlyIfConverterID;
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/// This pass performs instruction combining using trace metrics to estimate
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/// critical-path and resource depth.
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extern char &MachineCombinerID;
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/// StackSlotColoring - This pass performs stack coloring and merging.
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/// It merges disjoint allocas to reduce the stack size.
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extern char &StackColoringID;
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/// IfConverter - This pass performs machine code if conversion.
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extern char &IfConverterID;
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FunctionPass *createIfConverter(
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std::function<bool(const MachineFunction &)> Ftor);
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/// MachineBlockPlacement - This pass places basic blocks based on branch
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/// probabilities.
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extern char &MachineBlockPlacementID;
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/// MachineBlockPlacementStats - This pass collects statistics about the
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/// basic block placement using branch probabilities and block frequency
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/// information.
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extern char &MachineBlockPlacementStatsID;
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/// GCLowering Pass - Used by gc.root to perform its default lowering
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/// operations.
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FunctionPass *createGCLoweringPass();
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/// ShadowStackGCLowering - Implements the custom lowering mechanism
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/// used by the shadow stack GC. Only runs on functions which opt in to
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/// the shadow stack collector.
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FunctionPass *createShadowStackGCLoweringPass();
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/// GCMachineCodeAnalysis - Target-independent pass to mark safe points
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/// in machine code. Must be added very late during code generation, just
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/// prior to output, and importantly after all CFG transformations (such as
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/// branch folding).
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extern char &GCMachineCodeAnalysisID;
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/// Creates a pass to print GC metadata.
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///
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FunctionPass *createGCInfoPrinter(raw_ostream &OS);
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/// MachineCSE - This pass performs global CSE on machine instructions.
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extern char &MachineCSEID;
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/// ImplicitNullChecks - This pass folds null pointer checks into nearby
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/// memory operations.
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extern char &ImplicitNullChecksID;
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/// MachineLICM - This pass performs LICM on machine instructions.
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extern char &MachineLICMID;
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/// MachineSinking - This pass performs sinking on machine instructions.
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extern char &MachineSinkingID;
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/// MachineCopyPropagation - This pass performs copy propagation on
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/// machine instructions.
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extern char &MachineCopyPropagationID;
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/// PeepholeOptimizer - This pass performs peephole optimizations -
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/// like extension and comparison eliminations.
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extern char &PeepholeOptimizerID;
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/// OptimizePHIs - This pass optimizes machine instruction PHIs
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/// to take advantage of opportunities created during DAG legalization.
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extern char &OptimizePHIsID;
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/// StackSlotColoring - This pass performs stack slot coloring.
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extern char &StackSlotColoringID;
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/// \brief This pass lays out funclets contiguously.
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extern char &FuncletLayoutID;
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/// This pass inserts the XRay instrumentation sleds if they are supported by
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/// the target platform.
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extern char &XRayInstrumentationID;
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/// This pass inserts FEntry calls
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extern char &FEntryInserterID;
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/// \brief This pass implements the "patchable-function" attribute.
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extern char &PatchableFunctionID;
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/// createStackProtectorPass - This pass adds stack protectors to functions.
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///
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FunctionPass *createStackProtectorPass();
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/// createMachineVerifierPass - This pass verifies cenerated machine code
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/// instructions for correctness.
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///
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FunctionPass *createMachineVerifierPass(const std::string& Banner);
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/// createDwarfEHPass - This pass mulches exception handling code into a form
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/// adapted to code generation. Required if using dwarf exception handling.
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FunctionPass *createDwarfEHPass();
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/// createWinEHPass - Prepares personality functions used by MSVC on Windows,
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/// in addition to the Itanium LSDA based personalities.
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FunctionPass *createWinEHPass();
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/// createSjLjEHPreparePass - This pass adapts exception handling code to use
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/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
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///
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FunctionPass *createSjLjEHPreparePass();
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/// LocalStackSlotAllocation - This pass assigns local frame indices to stack
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/// slots relative to one another and allocates base registers to access them
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/// when it is estimated by the target to be out of range of normal frame
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/// pointer or stack pointer index addressing.
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extern char &LocalStackSlotAllocationID;
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/// ExpandISelPseudos - This pass expands pseudo-instructions.
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extern char &ExpandISelPseudosID;
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/// UnpackMachineBundles - This pass unpack machine instruction bundles.
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extern char &UnpackMachineBundlesID;
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FunctionPass *
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createUnpackMachineBundles(std::function<bool(const MachineFunction &)> Ftor);
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/// FinalizeMachineBundles - This pass finalize machine instruction
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/// bundles (created earlier, e.g. during pre-RA scheduling).
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extern char &FinalizeMachineBundlesID;
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/// StackMapLiveness - This pass analyses the register live-out set of
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/// stackmap/patchpoint intrinsics and attaches the calculated information to
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/// the intrinsic for later emission to the StackMap.
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extern char &StackMapLivenessID;
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/// LiveDebugValues pass
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extern char &LiveDebugValuesID;
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/// createJumpInstrTables - This pass creates jump-instruction tables.
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ModulePass *createJumpInstrTablesPass();
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/// createForwardControlFlowIntegrityPass - This pass adds control-flow
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/// integrity.
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ModulePass *createForwardControlFlowIntegrityPass();
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/// InterleavedAccess Pass - This pass identifies and matches interleaved
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/// memory accesses to target specific intrinsics.
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///
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FunctionPass *createInterleavedAccessPass();
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/// LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all
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/// TLS variables for the emulated TLS model.
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///
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ModulePass *createLowerEmuTLSPass();
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/// This pass lowers the @llvm.load.relative intrinsic to instructions.
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/// This is unsafe to do earlier because a pass may combine the constant
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/// initializer into the load, which may result in an overflowing evaluation.
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ModulePass *createPreISelIntrinsicLoweringPass();
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/// GlobalMerge - This pass merges internal (by default) globals into structs
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/// to enable reuse of a base pointer by indexed addressing modes.
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/// It can also be configured to focus on size optimizations only.
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///
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Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset,
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bool OnlyOptimizeForSize = false,
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bool MergeExternalByDefault = false);
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/// This pass splits the stack into a safe stack and an unsafe stack to
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/// protect against stack-based overflow vulnerabilities.
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FunctionPass *createSafeStackPass();
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/// This pass detects subregister lanes in a virtual register that are used
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/// independently of other lanes and splits them into separate virtual
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/// registers.
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extern char &RenameIndependentSubregsID;
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/// This pass is executed POST-RA to collect which physical registers are
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/// preserved by given machine function.
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FunctionPass *createRegUsageInfoCollector();
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/// Return a MachineFunction pass that identifies call sites
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/// and propagates register usage information of callee to caller
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/// if available with PysicalRegisterUsageInfo pass.
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FunctionPass *createRegUsageInfoPropPass();
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/// This pass performs software pipelining on machine instructions.
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extern char &MachinePipelinerID;
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/// This pass frees the memory occupied by the MachineFunction.
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FunctionPass *createFreeMachineFunctionPass();
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/// This pass performs outlining on machine instructions directly before
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/// printing assembly.
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ModulePass *createMachineOutlinerPass(bool OutlineFromLinkOnceODRs = false);
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/// This pass expands the experimental reduction intrinsics into sequences of
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/// shuffles.
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FunctionPass *createExpandReductionsPass();
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// This pass expands memcmp() to load/stores.
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FunctionPass *createExpandMemCmpPass();
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// This pass expands indirectbr instructions.
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FunctionPass *createIndirectBrExpandPass();
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} // End llvm namespace
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#endif
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