Files
archived-llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
Diana Picus 07b3834b44 [ARM] GlobalISel: Allow i8 and i16 adds
Teach the instruction selector and legalizer that it's ok to have adds with 8 or
16-bit integers.

This is the second part of https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290105 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:07:56 +00:00

45 lines
1.2 KiB
C++

//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file implements the targeting of the Machinelegalizer class for ARM.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
#include "ARMLegalizerInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h"
#include "llvm/Target/TargetOpcodes.h"
using namespace llvm;
#ifndef LLVM_BUILD_GLOBAL_ISEL
#error "You shouldn't build this"
#endif
ARMLegalizerInfo::ARMLegalizerInfo() {
using namespace TargetOpcode;
const LLT p0 = LLT::pointer(0, 32);
const LLT s8 = LLT::scalar(8);
const LLT s16 = LLT::scalar(16);
const LLT s32 = LLT::scalar(32);
setAction({G_FRAME_INDEX, p0}, Legal);
setAction({G_LOAD, s32}, Legal);
setAction({G_LOAD, 1, p0}, Legal);
for (auto Ty : {s8, s16, s32})
setAction({G_ADD, Ty}, Legal);
computeTables();
}