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------------------------------------------------------------------------ r312337 | nha | 2017-09-01 09:56:32 -0700 (Fri, 01 Sep 2017) | 12 lines AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states Summary: This fixes a bug that was exposed on gfx9 in various GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests, e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D36193 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314327 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
953 B
YAML
32 lines
953 B
YAML
# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
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# GCN: bb.0.entry:
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# GCN: %m0 = S_MOV_B32
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# GFX9: S_NOP 0
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# VI-NOT: S_NOP_0
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# GCN: V_INTERP_P1_F32
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---
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name: hazard_implicit_def
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '%sgpr7', virtual-reg: '' }
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- { reg: '%vgpr4', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: %sgpr7, %vgpr4
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%m0 = S_MOV_B32 killed %sgpr7
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%vgpr5 = IMPLICIT_DEF
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%vgpr0 = V_INTERP_P1_F32 killed %vgpr4, 0, 0, implicit %m0, implicit %exec
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SI_RETURN_TO_EPILOG killed %vgpr5, killed %vgpr0
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...
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