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db6cc311a0
This combine was already done in two places. The generic combiner already has done this since r217610, for adds (with a single use). This one was added in r303641, and added support for handling or as well. r313251 later added support to the generic combine for or. It also turns out the isOrEquivalentToAdd check is not necessary for this combine. Additionally, we already reproduce this combine in yet another place in the backend, although in that version multiple uses of the add are still folded if it will allow a fold into the addressing mode. That version needs to be improved to understand ors though, as well as the correct legal offsets for private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317526 91177308-0d34-0410-b5e6-96231b3b80d8
457 lines
16 KiB
C++
457 lines
16 KiB
C++
//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition of the TargetLowering class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
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#include "AMDGPU.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class AMDGPUMachineFunction;
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class AMDGPUSubtarget;
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struct ArgDescriptor;
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class AMDGPUTargetLowering : public TargetLowering {
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private:
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/// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
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/// legalized from a smaller type VT. Need to match pre-legalized type because
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/// the generic legalization inserts the add/sub between the select and
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/// compare.
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SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
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public:
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static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
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static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
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protected:
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const AMDGPUSubtarget *Subtarget;
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AMDGPUAS AMDGPUASI;
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Split a vector store into multiple scalar stores.
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/// \returns The resulting chain.
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SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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protected:
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bool shouldCombineMemoryType(EVT VT) const;
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SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
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unsigned Opc, SDValue LHS,
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uint32_t ValLo, uint32_t ValHi) const;
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SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
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SDValue RHS, DAGCombinerInfo &DCI) const;
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SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
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virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const;
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/// Return 64-bit value Op as two 32-bit integers.
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std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
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SelectionDAG &DAG) const;
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SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
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SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Split a vector load into 2 loads of half the vector.
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SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Split a vector store into 2 stores of half the vector.
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SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
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void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Results) const;
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void analyzeFormalArgumentsCompute(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) const;
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public:
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AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
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bool mayIgnoreSignedZero(SDValue Op) const {
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if (getTargetMachine().Options.NoSignedZerosFPMath)
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return true;
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const auto Flags = Op.getNode()->getFlags();
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if (Flags.isDefined())
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return Flags.hasNoSignedZeros();
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return false;
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}
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static bool allUsesHaveSourceMods(const SDNode *N,
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unsigned CostThreshold = 4);
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bool isFAbsFree(EVT VT) const override;
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bool isFNegFree(EVT VT) const override;
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bool isTruncateFree(EVT Src, EVT Dest) const override;
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bool isTruncateFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(EVT Src, EVT Dest) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
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bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
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MVT getVectorIdxTy(const DataLayout &) const override;
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bool isSelectSupported(SelectSupportKind) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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bool ShouldShrinkFPConstant(EVT VT) const override;
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bool shouldReduceLoadWidth(SDNode *Load,
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ISD::LoadExtType ExtType,
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EVT ExtVT) const override;
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bool isLoadBitCastBeneficial(EVT, EVT) const final;
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bool storeOfVectorConstantIsCheap(EVT MemVT,
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unsigned NumElem,
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unsigned AS) const override;
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bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
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static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue addTokenForArgument(SDValue Chain,
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SelectionDAG &DAG,
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MachineFrameInfo &MFI,
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int ClobberedFI) const;
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SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals,
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StringRef Reason) const;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
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SelectionDAG &DAG) const;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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void ReplaceNodeResults(SDNode * N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
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SDValue RHS, SDValue True, SDValue False,
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SDValue CC, DAGCombinerInfo &DCI) const;
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const char* getTargetNodeName(unsigned Opcode) const override;
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bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
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return true;
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}
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SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
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int &RefinementSteps, bool &UseOneConstNR,
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bool Reciprocal) const override;
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SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
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int &RefinementSteps) const override;
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virtual SDNode *PostISelFolding(MachineSDNode *N,
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SelectionDAG &DAG) const = 0;
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/// \brief Determine which of the bits specified in \p Mask are known to be
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/// either zero or one and return them in the \p KnownZero and \p KnownOne
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/// bitsets.
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void computeKnownBitsForTargetNode(const SDValue Op,
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KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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/// \brief Helper function that adds Reg to the LiveIn list of the DAG's
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/// MachineFunction.
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///
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/// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
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/// a copy from the register.
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SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT,
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const SDLoc &SL,
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bool RawReg = false) const;
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SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
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}
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// Returns the raw live in register rather than a copy from it.
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SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
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}
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/// Similar to CreateLiveInRegister, except value maybe loaded from a stack
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/// slot rather than passed in a register.
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SDValue loadStackInputValue(SelectionDAG &DAG,
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EVT VT,
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const SDLoc &SL,
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int64_t Offset) const;
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SDValue storeStackInputValue(SelectionDAG &DAG,
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const SDLoc &SL,
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SDValue Chain,
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SDValue StackPtr,
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SDValue ArgVal,
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int64_t Offset) const;
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SDValue loadInputValue(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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EVT VT, const SDLoc &SL,
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const ArgDescriptor &Arg) const;
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enum ImplicitParameter {
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FIRST_IMPLICIT,
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GRID_DIM = FIRST_IMPLICIT,
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GRID_OFFSET,
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};
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/// \brief Helper function that returns the byte offset of the given
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/// type of implicit parameter.
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uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
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const ImplicitParameter Param) const;
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AMDGPUAS getAMDGPUAS() const {
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return AMDGPUASI;
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}
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MVT getFenceOperandTy(const DataLayout &DL) const override {
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return MVT::i32;
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}
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};
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namespace AMDGPUISD {
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enum NodeType : unsigned {
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// AMDIL ISD Opcodes
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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UMUL, // 32bit unsigned multiplication
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BRANCH_COND,
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// End AMDIL ISD Opcodes
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// Function call.
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CALL,
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TC_RETURN,
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TRAP,
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// Masked control flow nodes.
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IF,
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ELSE,
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LOOP,
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// A uniform kernel return that terminates the wavefront.
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ENDPGM,
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// Return to a shader part's epilog code.
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RETURN_TO_EPILOG,
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// Return with values from a non-entry function.
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RET_FLAG,
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DWORDADDR,
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FRACT,
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/// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
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/// modifier behavior with dx10_enable.
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CLAMP,
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// This is SETCC with the full mask result which is used for a compare with a
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// result bit per item in the wavefront.
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SETCC,
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SETREG,
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// FP ops with input and output chain.
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FMA_W_CHAIN,
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FMUL_W_CHAIN,
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// SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
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// Denormals handled on some parts.
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COS_HW,
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SIN_HW,
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FMAX_LEGACY,
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FMIN_LEGACY,
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FMAX3,
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SMAX3,
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UMAX3,
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FMIN3,
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SMIN3,
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UMIN3,
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FMED3,
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SMED3,
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UMED3,
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URECIP,
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DIV_SCALE,
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DIV_FMAS,
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DIV_FIXUP,
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// For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
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// treated as an illegal operation.
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FMAD_FTZ,
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TRIG_PREOP, // 1 ULP max error for f64
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// RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
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// For f64, max error 2^29 ULP, handles denormals.
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RCP,
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RSQ,
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RCP_LEGACY,
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RSQ_LEGACY,
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FMUL_LEGACY,
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RSQ_CLAMP,
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LDEXP,
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FP_CLASS,
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DOT4,
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CARRY,
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BORROW,
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BFE_U32, // Extract range of bits with zero extension to 32-bits.
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BFE_I32, // Extract range of bits with sign extension to 32-bits.
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BFI, // (src0 & src1) | (~src0 & src2)
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BFM, // Insert a range of bits into a 32-bit word.
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FFBH_U32, // ctlz with -1 if input is zero.
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FFBH_I32,
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FFBL_B32, // cttz with -1 if input is zero.
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MUL_U24,
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MUL_I24,
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MULHI_U24,
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MULHI_I24,
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MAD_U24,
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MAD_I24,
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MAD_U64_U32,
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MAD_I64_I32,
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MUL_LOHI_I24,
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MUL_LOHI_U24,
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TEXTURE_FETCH,
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EXPORT, // exp on SI+
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EXPORT_DONE, // exp on SI+ with done bit set
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R600_EXPORT,
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CONST_ADDRESS,
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REGISTER_LOAD,
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REGISTER_STORE,
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SAMPLE,
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SAMPLEB,
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SAMPLED,
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SAMPLEL,
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// These cvt_f32_ubyte* nodes need to remain consecutive and in order.
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CVT_F32_UBYTE0,
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CVT_F32_UBYTE1,
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CVT_F32_UBYTE2,
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CVT_F32_UBYTE3,
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// Convert two float 32 numbers into a single register holding two packed f16
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// with round to zero.
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CVT_PKRTZ_F16_F32,
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// Same as the standard node, except the high bits of the resulting integer
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// are known 0.
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FP_TO_FP16,
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// Wrapper around fp16 results that are known to zero the high bits.
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FP16_ZEXT,
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/// This node is for VLIW targets and it is used to represent a vector
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/// that is stored in consecutive registers with the same channel.
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/// For example:
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/// |X |Y|Z|W|
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/// T0|v.x| | | |
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/// T1|v.y| | | |
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/// T2|v.z| | | |
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/// T3|v.w| | | |
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BUILD_VERTICAL_VECTOR,
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/// Pointer to the start of the shader's constant data.
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CONST_DATA_PTR,
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INIT_EXEC,
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INIT_EXEC_FROM_INPUT,
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SENDMSG,
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SENDMSGHALT,
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INTERP_MOV,
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INTERP_P1,
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INTERP_P2,
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PC_ADD_REL_OFFSET,
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KILL,
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DUMMY_CHAIN,
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FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
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STORE_MSKOR,
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LOAD_CONSTANT,
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TBUFFER_STORE_FORMAT,
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TBUFFER_STORE_FORMAT_X3,
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TBUFFER_LOAD_FORMAT,
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ATOMIC_CMP_SWAP,
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ATOMIC_INC,
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ATOMIC_DEC,
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BUFFER_LOAD,
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BUFFER_LOAD_FORMAT,
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LAST_AMDGPU_ISD_NUMBER
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};
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} // End namespace AMDGPUISD
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} // End namespace llvm
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#endif
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