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a15bb16493
Using SplitCSR for the frame register was very broken. Often the copies in the prolog and epilog were optimized out, in addition to them being inserted after the true prolog where the FP was clobbered. I have a hacky solution which works that continues to use split CSR, but for now this is simpler and will get to working programs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313274 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
2.6 KiB
LLVM
109 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -enable-ipra -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN %s
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; Kernels are not called, so there is no call preserved mask.
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; GCN-LABEL: {{^}}kernel:
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; GCN: flat_store_dword
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define amdgpu_kernel void @kernel(i32 addrspace(1)* %out) #0 {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}func:
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; GCN: ; NumVgprs: 8
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define void @func() #1 {
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call:
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_load_dword v8
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
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; GCN: ; NumSgprs: 37
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; GCN: ; NumVgprs: 9
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define amdgpu_kernel void @kernel_call() #0 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}func_regular_call:
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_load_dword v8
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
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; GCN: ; NumSgprs: 32
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; GCN: ; NumVgprs: 9
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define void @func_regular_call() #1 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}func_tail_call:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64 s[6:7]
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; GCN-NEXT: s_add_u32 s6,
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; GCN-NEXT: s_addc_u32 s7,
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; GCN-NEXT: s_setpc_b64 s[6:7]
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; GCN: ; NumSgprs: 32
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; GCN: ; NumVgprs: 8
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define void @func_tail_call() #1 {
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tail call void @func()
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ret void
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}
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; GCN-LABEL: {{^}}func_call_tail_call:
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; GCN: flat_load_dword v8
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; GCN: s_swappc_b64
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
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; GCN: s_setpc_b64
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; GCN: ; NumSgprs: 32
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; GCN: ; NumVgprs: 9
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define void @func_call_tail_call() #1 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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tail call void @func()
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ret void
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}
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define void @void_func_void() noinline {
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ret void
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}
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; Make sure we don't get save/restore of FP between calls.
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; GCN-LABEL: {{^}}test_funcx2:
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; GCN-NOT: s5
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; GCN-NOT: s32
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define void @test_funcx2() #0 {
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call void @void_func_void()
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call void @void_func_void()
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind noinline }
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