Files
archived-llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
Justin Bogner edab757966 MIR: Print the register class or bank in vreg defs
This updates the MIRPrinter to include the regclass when printing
virtual register defs, which is already valid syntax for the
parser. That is, given 64 bit %0 and %1 in a "gpr" regbank,

  %1(s64) = COPY %0(s64)

would now be written as

  %1:gpr(s64) = COPY %0(s64)

While this change alone introduces a bit of redundancy with the
registers block, it allows us to update the tests to be more concise
and understandable and brings us closer to being able to remove the
registers block completely.

Note: We generally only print the class in defs, but there is one
exception. If there are uses without any defs whatsoever, we'll print
the class on all uses. I'm not completely convinced this comes up in
meaningful machine IR, but for now the MIRParser and MachineVerifier
both accept that kind of stuff, so we don't want to have a situation
where we can print something we can't parse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24 18:04:54 +00:00

191 lines
5.0 KiB
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# RUN: llc -march=amdgcn %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: test_madmk_reg_imm_f32
# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit %exec
---
name: test_madmk_reg_imm_f32
registers:
- { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
body: |
bb.0:
%0 = IMPLICIT_DEF
%1 = COPY %0.sub1
%2 = V_MOV_B32_e32 1078523331, implicit %exec
%3 = V_MAC_F32_e32 killed %0.sub0, %2, killed %1, implicit %exec
...
# GCN-LABEL: name: test_madmk_imm_reg_f32
# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit %exec
---
name: test_madmk_imm_reg_f32
registers:
- { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
body: |
bb.0:
%0 = IMPLICIT_DEF
%1 = COPY %0.sub1
%2 = V_MOV_B32_e32 1078523331, implicit %exec
%3 = V_MAC_F32_e32 %2, killed %0.sub0, killed %1, implicit %exec
...
# GCN-LABEL: name: test_madak_f32
# GCN: V_MADAK_F32 killed %0.sub0, %0.sub1, 1078523331, implicit %exec
---
name: test_madak_f32
registers:
- { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
body: |
bb.0:
%0 = IMPLICIT_DEF
%1 = V_MOV_B32_e32 1078523331, implicit %exec
%2 = V_MAC_F32_e32 killed %0.sub0, %0.sub1, %1, implicit %exec
...
# GCN-LABEL: name: test_madmk_reg_imm_f16
# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit %exec
---
name: test_madmk_reg_imm_f16
registers:
- { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
body: |
bb.0:
%0 = IMPLICIT_DEF
%1 = COPY %0.sub1
%2 = V_MOV_B32_e32 1078523331, implicit %exec
%3 = V_MAC_F16_e32 killed %0.sub0, %2, killed %1, implicit %exec
...
# GCN-LABEL: name: test_madmk_imm_reg_f16
# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit %exec
---
name: test_madmk_imm_reg_f16
registers:
- { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
body: |
bb.0:
%0 = IMPLICIT_DEF
%1 = COPY %0.sub1
%2 = V_MOV_B32_e32 1078523331, implicit %exec
%3 = V_MAC_F16_e32 %2, killed %0.sub0, killed %1, implicit %exec
...
# GCN-LABEL: name: test_madak_f16
# GCN: V_MADAK_F16 killed %0.sub0, %0.sub1, 1078523331, implicit %exec
---
name: test_madak_f16
registers:
- { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
body: |
bb.0:
%0 = IMPLICIT_DEF
%1 = V_MOV_B32_e32 1078523331, implicit %exec
%2 = V_MAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit %exec
...
# Make sure constant bus restriction isn't violated if src0 is an SGPR.
# GCN-LABEL: name: test_madak_sgpr_src0_f32
# GCN: %1:vgpr_32 = V_MOV_B32_e32 1078523331, implicit %exec
# GCN: %2:vgpr_32 = V_MAD_F32 0, killed %0, 0, %1, 0, %3:vgpr_32, 0, 0, implicit %exec
---
name: test_madak_sgpr_src0_f32
registers:
- { id: 0, class: sreg_32_xm0 }
- { id: 1, class: vgpr_32}
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
body: |
bb.0:
%0 = IMPLICIT_DEF
%1 = V_MOV_B32_e32 1078523331, implicit %exec
%2 = V_MAC_F32_e32 killed %0, %1, %3, implicit %exec
...
# This can still fold if this is an inline immediate.
# GCN-LABEL: name: test_madak_inlineimm_src0_f32
# GCN: %1:vgpr_32 = V_MADMK_F32 1073741824, 1078523331, %2:vgpr_32, implicit %exec
---
name: test_madak_inlineimm_src0_f32
registers:
- { id: 0, class: vgpr_32}
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
body: |
bb.0:
%0 = V_MOV_B32_e32 1078523331, implicit %exec
%1 = V_MAC_F32_e32 1073741824, %0, %2, implicit %exec
...
# Non-inline immediate uses constant bus already.
# GCN-LABEL: name: test_madak_otherimm_src0_f32
# GCN: %1:vgpr_32 = V_MAC_F32_e32 1120403456, %0, %1, implicit %exec
---
name: test_madak_otherimm_src0_f32
registers:
- { id: 0, class: vgpr_32}
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
body: |
bb.0:
%0 = V_MOV_B32_e32 1078523331, implicit %exec
%1 = V_MAC_F32_e32 1120403456, %0, %2, implicit %exec
...
# Non-inline immediate uses constant bus already.
# GCN-LABEL: name: test_madak_other_constantlike_src0_f32
# GCN: %1:vgpr_32 = V_MAC_F32_e32 %stack.0, %0, %1, implicit %exec
---
name: test_madak_other_constantlike_src0_f32
registers:
- { id: 0, class: vgpr_32}
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
stack:
- { id: 0, name: "", type: default, offset: 0, size: 128, alignment: 8,
callee-saved-register: '', local-offset: 0, di-variable: '', di-expression: '',
di-location: '' }
body: |
bb.0:
%0 = V_MOV_B32_e32 1078523331, implicit %exec
%1 = V_MAC_F32_e32 %stack.0, %0, %2, implicit %exec
...