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ee9c80e579
This patch complements D16810 "[mips] Make isel select the correct DEXT variant up front.". Now ISel picks the right variant of DINS, so now there is no need to replace DINS with the appropriate variant during MipsMCCodeEmitter::encodeInstruction(). This patch also enables target specific instruction verification for ins, dins, dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these constraints are not checked during instruction selection. Adding machine verification should catch outstanding cases. Finally, correct a bug that instruction verification uncovered, where the position operand of a DINSU generated during lowering was being silently and accidently corrected to the correct value. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34809 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313254 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
2.1 KiB
LLVM
61 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
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; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2
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define double @func0(double %d0, double %d1) nounwind readnone {
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entry:
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;
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; 32: lui $[[MSK1:[0-9]+]], 32768
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; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 32: mtc1 $[[OR]], $f1
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; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
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; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
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; 32R2: mthc1 $[[INS]], $f0
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; 64: daddiu $[[T0:[0-9]+]], $zero, 1
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; 64: dsll $[[MSK1:[0-9]+]], $[[T0]], 63
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; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 64: daddiu $[[MSK0:[0-9]+]], $[[MSK1]], -1
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; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 64: dmtc1 $[[OR]], $f0
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; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
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; 64R2: dinsu $[[INS:[0-9]+]], $[[EXT]], 63, 1
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; 64R2: dmtc1 $[[INS]], $f0
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%call = tail call double @copysign(double %d0, double %d1) nounwind readnone
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ret double %call
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}
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declare double @copysign(double, double) nounwind readnone
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define float @func1(float %f0, float %f1) nounwind readnone {
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entry:
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; 32: lui $[[MSK1:[0-9]+]], 32768
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; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 32: mtc1 $[[OR]], $f0
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; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
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; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
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; 32R2: mtc1 $[[INS]], $f0
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%call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
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ret float %call
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}
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declare float @copysignf(float, float) nounwind readnone
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