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559fb26604
In the past while, I've committed a number of patches in the PowerPC back end aimed at eliminating comparison instructions. However, this causes some failures in proprietary source and these issues are not observed in SPEC or any open source packages I've been able to run. As a result, I'm pulling the entire series and will refactor it to: - Have a single entry point for easy control - Have fine-grained control over which patterns we transform A side-effect of this is that test cases for these patches (and modified by them) are XFAIL-ed. This is a temporary measure as it is counter-productive to remove/modify these test cases and then have to modify them again when the refactored patch is recommitted. The failure will be investigated in parallel to the refactoring effort and the recommit will either have a fix for it or will leave this transformation off by default until the problem is resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314244 91177308-0d34-0410-b5e6-96231b3b80d8
136 lines
4.2 KiB
LLVM
136 lines
4.2 KiB
LLVM
; XFAIL: *
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i64 0, align 8
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
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; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
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; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: xori r3, [[REG4]], 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_sext:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
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; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
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; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK-NEXT: neg r3, [[REG5]]
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; FIXME
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_z(i64 %a) {
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; CHECK-LABEL: test_igtsll_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: nor r3, r4, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_sext_z(i64 %a) {
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; CHECK-LABEL: test_igtsll_sext_z:
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; CHECK: addi [[REG1:r[0-9]+]], r3, -1
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; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3
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; CHECK-NEXT: sradi r3, [[REG2]], 63
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entry:
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%cmp = icmp sgt i64 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
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; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
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; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
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; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK-NOT: neg
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_sext_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
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; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
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; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
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; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK: neg {{r[0-9]+}}, [[REG5]]
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; FIXME
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_z_store(i64 %a) {
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; CHECK-LABEL: test_igtsll_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: addi r5, r3, -1
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: nor r3, r5, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_igtsll_sext_z_store:
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; CHECK: addi [[REG1:r[0-9]+]], r3, -1
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; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3
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; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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