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559fb26604
In the past while, I've committed a number of patches in the PowerPC back end aimed at eliminating comparison instructions. However, this causes some failures in proprietary source and these issues are not observed in SPEC or any open source packages I've been able to run. As a result, I'm pulling the entire series and will refactor it to: - Have a single entry point for easy control - Have fine-grained control over which patterns we transform A side-effect of this is that test cases for these patches (and modified by them) are XFAIL-ed. This is a temporary measure as it is counter-productive to remove/modify these test cases and then have to modify them again when the refactored patch is recommitted. The failure will be investigated in parallel to the refactoring effort and the recommit will either have a fix for it or will leave this transformation off by default until the problem is resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314244 91177308-0d34-0410-b5e6-96231b3b80d8
139 lines
3.9 KiB
LLVM
139 lines
3.9 KiB
LLVM
; XFAIL: *
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i16 0, align 2
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define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_ineus:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_ineus_sext:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define signext i32 @test_ineus_z(i16 zeroext %a) {
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; CHECK-LABEL: test_ineus_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, 0
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%conv1 = zext i1 %cmp to i32
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ret i32 %conv1
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}
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define signext i32 @test_ineus_sext_z(i16 zeroext %a) {
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; CHECK-LABEL: test_ineus_sext_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_ineus_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, %b
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%conv3 = zext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_ineus_sext_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, %b
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%conv3 = sext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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define void @test_ineus_z_store(i16 zeroext %a) {
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; CHECK-LABEL: test_ineus_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, 0
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%conv2 = zext i1 %cmp to i16
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store i16 %conv2, i16* @glob, align 2
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ret void
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}
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define void @test_ineus_sext_z_store(i16 zeroext %a) {
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; CHECK-LABEL: test_ineus_sext_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, 0
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%conv2 = sext i1 %cmp to i16
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store i16 %conv2, i16* @glob, align 2
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ret void
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}
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