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The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315063 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
669 B
LLVM
21 lines
669 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=zEC12 -o - %s | FileCheck %s
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target triple = "s390x-ibm-linux"
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define <2 x float> @pr32505(<2 x i8> * %a) {
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; CHECK-LABEL: pr32505:
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; CHECK: # BB#0:
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; CHECK-NEXT: lbh %r0, 1(%r2)
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; CHECK-NEXT: lbh %r1, 0(%r2)
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; CHECK-NEXT: ldgr %f0, %r1
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; CHECK-NEXT: ldgr %f2, %r0
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; CHECK-NEXT: # kill: %F0S<def> %F0S<kill> %F0D<kill>
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; CHECK-NEXT: # kill: %F2S<def> %F2S<kill> %F2D<kill>
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; CHECK-NEXT: br %r14
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%L17 = load <2 x i8>, <2 x i8>* %a
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%Se21 = sext <2 x i8> %L17 to <2 x i32>
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%BC = bitcast <2 x i32> %Se21 to <2 x float>
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ret <2 x float> %BC
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}
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