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726d93c06c
Summary: This suppresses the generation of .Lcfi labels in our textual assembler. It was annoying that this generated cascading .Lcfi labels: llc foo.ll -o - | llvm-mc | llvm-mc After three trips through MCAsmStreamer, we'd have three labels in the output when none are necessary. We should only bother creating the labels and frame data when making a real object file. This supercedes D38605, which moved the entire .seh_ implementation into MCObjectStreamer. This has the advantage that we do more checking when emitting textual assembly, as a minor efficiency cost. Outputting textual assembly is not performance critical, so this shouldn't matter. Reviewers: majnemer, MatzeB Subscribers: qcolombet, nemanjai, javed.absar, eraman, hiraditya, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D38638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315259 91177308-0d34-0410-b5e6-96231b3b80d8
364 lines
12 KiB
LLVM
364 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
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@var = global i128 0
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; Due to the scheduling right after isel for cmpxchg and given the
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; machine scheduler and copy coalescer do not mess up with physical
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; register live-ranges, we end up with a useless copy.
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define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
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; CHECK-LABEL: val_compare_and_swap:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rcx, %r9
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: movq %r9, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
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%val = extractvalue { i128, i1 } %pair, 0
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ret i128 %val
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}
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define void @fetch_and_nand(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_nand:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB1_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: andq %r8, %rcx
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; CHECK-NEXT: movq %rax, %rbx
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; CHECK-NEXT: andq %rsi, %rbx
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; CHECK-NEXT: notq %rbx
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; CHECK-NEXT: notq %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB1_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%val = atomicrmw nand i128* %p, i128 %bits release
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_or(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_or:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB2_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rax, %rbx
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; CHECK-NEXT: orq %rsi, %rbx
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: orq %r8, %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB2_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%val = atomicrmw or i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_add(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_add:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB3_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rax, %rbx
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; CHECK-NEXT: addq %rsi, %rbx
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: adcq %r8, %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB3_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%val = atomicrmw add i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_sub(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_sub:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB4_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rax, %rbx
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; CHECK-NEXT: subq %rsi, %rbx
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: sbbq %r8, %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB4_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%val = atomicrmw sub i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_min(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_min:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB5_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpq %rax, %rsi
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: sbbq %rdx, %rcx
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: cmovgeq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: cmovgeq %rax, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB5_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%val = atomicrmw min i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_max(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_max:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB6_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpq %rsi, %rax
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: sbbq %r8, %rcx
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: cmovgeq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: cmovgeq %rax, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB6_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%val = atomicrmw max i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_umin(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_umin:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB7_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpq %rax, %rsi
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: sbbq %rdx, %rcx
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: cmovaeq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: cmovaeq %rax, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB7_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%val = atomicrmw umin i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_umax(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_umax:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB8_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpq %rax, %rsi
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: sbbq %rdx, %rcx
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: cmovbq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: cmovbq %rax, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB8_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%val = atomicrmw umax i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define i128 @atomic_load_seq_cst(i128* %p) {
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; CHECK-LABEL: atomic_load_seq_cst:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: xorl %ebx, %ebx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%r = load atomic i128, i128* %p seq_cst, align 16
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ret i128 %r
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}
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define i128 @atomic_load_relaxed(i128* %p) {
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; CHECK-LABEL: atomic_load_relaxed:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: xorl %ebx, %ebx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%r = load atomic i128, i128* %p monotonic, align 16
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ret i128 %r
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}
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define void @atomic_store_seq_cst(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_seq_cst:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB11_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB11_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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store atomic i128 %in, i128* %p seq_cst, align 16
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ret void
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}
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define void @atomic_store_release(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_release:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB12_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB12_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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store atomic i128 %in, i128* %p release, align 16
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ret void
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}
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define void @atomic_store_relaxed(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_relaxed:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB13_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB13_1
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; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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store atomic i128 %in, i128* %p unordered, align 16
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ret void
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}
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