Tim Northover 97c0826552 ARM: use a pseudo-instruction for cmpxchg at -O0. ...

The fast register-allocator cannot cope with inter-block dependencies without
spilling. This is fine for ldrex/strex loops coming from atomicrmw instructions
where any value produced within a block is dead by the end, but not for
cmpxchg. So we lower a cmpxchg at -O0 via a pseudo-inst that gets expanded
after regalloc.

Fortunately this is at -O0 so we don't have to care about performance. This
simplifies the various axes of expansion considerably: we assume a strong
seq_cst operation and ensure ordering via the always-present DMB instructions
rather than v8 acquire/release instructions.

Should fix the 32-bit part of PR25526.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266679 91177308-0d34-0410-b5e6-96231b3b80d8

2016-04-18 21:48:55 +00:00

..

atomic-expansion-v7.ll

ARM: use a pseudo-instruction for cmpxchg at -O0.

2016-04-18 21:48:55 +00:00

atomic-expansion-v8.ll

ARM: use a pseudo-instruction for cmpxchg at -O0.

2016-04-18 21:48:55 +00:00

cmpxchg-weak.ll

ARM: use a pseudo-instruction for cmpxchg at -O0.

2016-04-18 21:48:55 +00:00

lit.local.cfg

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