Files
archived-llvm/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll
Sanjay Patel 72428f5e04 [SimplifyCFG] use pass options and remove the latesimplifycfg pass
This is no-functional-change-intended.

This is repackaging the functionality of D30333 (defer switch-to-lookup-tables) and 
D35411 (defer folding unconditional branches) with pass parameters rather than a named
"latesimplifycfg" pass. Now that we have individual options to control the functionality,
we could decouple when these fire (but that's an independent patch if desired). 

The next planned step would be to add another option bit to disable the sinking transform
mentioned in D38566. This should also make it clear that the new pass manager needs to
be updated to limit simplifycfg in the same way as the old pass manager.

Differential Revision: https://reviews.llvm.org/D38631



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316835 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-28 18:43:07 +00:00

42 lines
1.4 KiB
LLVM

; RUN: opt -S -simplifycfg -switch-to-lookup < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
; rdar://17735071
target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin12.0.0"
; When tableindex can't fit into i2, we should extend the type to i3.
; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si
; CHECK: entry:
; CHECK-NEXT: sub i2 %0, -2
; CHECK-NEXT: zext i2 %switch.tableidx to i3
; CHECK-NEXT: getelementptr inbounds [4 x i64], [4 x i64]* @switch.table._TFO6reduce1E5toRawfS0_FT_Si, i32 0, i3 %switch.tableidx.zext
; CHECK-NEXT: load i64, i64* %switch.gep
; CHECK-NEXT: ret i64 %switch.load
define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) {
entry:
switch i2 %0, label %1 [
i2 0, label %2
i2 1, label %3
i2 -2, label %4
i2 -1, label %5
]
; <label>:1 ; preds = %entry
unreachable
; <label>:2 ; preds = %2
br label %6
; <label>:3 ; preds = %4
br label %6
; <label>:4 ; preds = %6
br label %6
; <label>:5 ; preds = %8
br label %6
; <label>:6 ; preds = %3, %5, %7, %9
%7 = phi i64 [ 3, %5 ], [ 2, %4 ], [ 1, %3 ], [ 0, %2 ]
ret i64 %7
}