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Support for 64-bit coprocessors on a 32-bit architecture was added in `MIPS32 R2`. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365507 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
994 B
LLVM
35 lines
994 B
LLVM
; A basic inline assembly test
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; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
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@v4i32_r = global <4 x i32> zeroinitializer, align 16
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define void @test1() nounwind {
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entry:
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; CHECK-LABEL: test1:
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%0 = call <4 x i32> asm "ldi.w ${0:w}, 1", "=f"()
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; CHECK: ldi.w $w{{[1-3]?[0-9]}}, 1
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store <4 x i32> %0, <4 x i32>* @v4i32_r
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ret void
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}
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define void @test2() nounwind {
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entry:
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; CHECK-LABEL: test2:
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%0 = load <4 x i32>, <4 x i32>* @v4i32_r
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%1 = call <4 x i32> asm "addvi.w ${0:w}, ${1:w}, 1", "=f,f"(<4 x i32> %0)
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; CHECK: addvi.w $w{{[1-3]?[0-9]}}, $w{{[1-3]?[0-9]}}, 1
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store <4 x i32> %1, <4 x i32>* @v4i32_r
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ret void
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}
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define void @test3() nounwind {
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entry:
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; CHECK-LABEL: test3:
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%0 = load <4 x i32>, <4 x i32>* @v4i32_r
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%1 = call <4 x i32> asm sideeffect "addvi.w ${0:w}, ${1:w}, 1", "=f,f,~{$w0}"(<4 x i32> %0)
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; CHECK: addvi.w $w{{([1-9]|[1-3][0-9])}}, $w{{([1-9]|[1-3][0-9])}}, 1
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store <4 x i32> %1, <4 x i32>* @v4i32_r
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ret void
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}
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