Hal Finkel 0ef99720c5 [PowerPC] Remove zexts after byte-swapping loads ...

lhbrx and lwbrx not only load their data with byte swapping, but also clear the
upper 32 bits (at least). As a result, they can be added to the PPCISelDAGToDAG
peephole optimization as frontier instructions for the removal of unnecessary
zero extensions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225189 91177308-0d34-0410-b5e6-96231b3b80d8

2015-01-05 18:09:06 +00:00

..

AArch64

[AArch64] Improve codegen of store lane instructions by avoiding GPR usage.

2015-01-05 17:10:26 +00:00

ARM

Emit the build attribute Tag_conformance.

2015-01-05 13:12:17 +00:00

CPP

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Generic

CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.

2014-12-19 20:50:07 +00:00

Hexagon

[Hexagon] Adding reg-reg indexed load forms.

2014-12-30 18:58:47 +00:00

Inputs

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

Mips

[mips][microMIPS] Fix bugs related to atomic SC/LL instructions

2014-12-18 16:39:29 +00:00

MSP430

Drop the W postfix on the 16-bit registers.

2014-09-10 06:58:14 +00:00

NVPTX

[NVPTX] Fix bugs related to isSingleValueType

2014-12-17 17:59:04 +00:00

PowerPC

[PowerPC] Remove zexts after byte-swapping loads

2015-01-05 18:09:06 +00:00

R600

Enable (sext x) == C --> x == (trunc C) combine

2014-12-21 16:48:42 +00:00

SPARC

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

SystemZ

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

Thumb

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

Thumb2

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

X86

[X86][SSE] Added vector packing test for pr12412

2015-01-04 19:08:03 +00:00

XCore

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00