mirror of
https://github.com/RPCS3/llvm.git
synced 2026-01-31 01:25:19 +01:00
b2823d3d6d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295460 91177308-0d34-0410-b5e6-96231b3b80d8
475 lines
12 KiB
LLVM
475 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mattr=+isel | FileCheck %s --check-prefix=ALL --check-prefix=ISEL
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; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mattr=-isel | FileCheck %s --check-prefix=ALL --check-prefix=NO_ISEL
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; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).
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; Test the zeroext/signext variants of each pattern to see if that makes a difference.
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; select Cond, 0, 1 --> zext (!Cond)
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define i32 @select_0_or_1(i1 %cond) {
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; ALL-LABEL: select_0_or_1:
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; ALL: # BB#0:
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; ALL-NEXT: not 3, 3
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; ALL-NEXT: clrldi 3, 3, 63
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; ALL-NEXT: blr
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {
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; ALL-LABEL: select_0_or_1_zeroext:
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; ALL: # BB#0:
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; ALL-NEXT: xori 3, 3, 1
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; ALL-NEXT: blr
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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define i32 @select_0_or_1_signext(i1 signext %cond) {
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; ALL-LABEL: select_0_or_1_signext:
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; ALL: # BB#0:
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; ALL-NEXT: not 3, 3
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; ALL-NEXT: clrldi 3, 3, 63
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; ALL-NEXT: blr
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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; select Cond, 1, 0 --> zext (Cond)
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define i32 @select_1_or_0(i1 %cond) {
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; ISEL-LABEL: select_1_or_0:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 1
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; ISEL-NEXT: li 3, 0
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_1_or_0:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 1
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; NO_ISEL-NEXT: li 3, 0
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; NO_ISEL-NEXT: bc 12, 1, .LBB3_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB3_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
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; ISEL-LABEL: select_1_or_0_zeroext:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 1
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; ISEL-NEXT: li 3, 0
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_1_or_0_zeroext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 1
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; NO_ISEL-NEXT: li 3, 0
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; NO_ISEL-NEXT: bc 12, 1, .LBB4_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB4_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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define i32 @select_1_or_0_signext(i1 signext %cond) {
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; ISEL-LABEL: select_1_or_0_signext:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 1
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; ISEL-NEXT: li 3, 0
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_1_or_0_signext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 1
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; NO_ISEL-NEXT: li 3, 0
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; NO_ISEL-NEXT: bc 12, 1, .LBB5_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB5_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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; select Cond, 0, -1 --> sext (!Cond)
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define i32 @select_0_or_neg1(i1 %cond) {
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; ISEL-LABEL: select_0_or_neg1:
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; ISEL: # BB#0:
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; ISEL-NEXT: li 4, 0
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: oris 3, 4, 65535
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; ISEL-NEXT: ori 3, 3, 65535
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; ISEL-NEXT: isel 3, 0, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_0_or_neg1:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: li 4, 0
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: oris 3, 4, 65535
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; NO_ISEL-NEXT: ori 3, 3, 65535
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; NO_ISEL-NEXT: bc 12, 1, .LBB6_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB6_1:
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; NO_ISEL-NEXT: addi 3, 0, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
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; ISEL-LABEL: select_0_or_neg1_zeroext:
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; ISEL: # BB#0:
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; ISEL-NEXT: li 4, 0
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: oris 3, 4, 65535
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; ISEL-NEXT: ori 3, 3, 65535
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; ISEL-NEXT: isel 3, 0, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_0_or_neg1_zeroext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: li 4, 0
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: oris 3, 4, 65535
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; NO_ISEL-NEXT: ori 3, 3, 65535
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; NO_ISEL-NEXT: bc 12, 1, .LBB7_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB7_1:
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; NO_ISEL-NEXT: addi 3, 0, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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define i32 @select_0_or_neg1_signext(i1 signext %cond) {
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; ISEL-LABEL: select_0_or_neg1_signext:
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; ISEL: # BB#0:
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; ISEL-NEXT: li 4, 0
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: oris 3, 4, 65535
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; ISEL-NEXT: ori 3, 3, 65535
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; ISEL-NEXT: isel 3, 0, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_0_or_neg1_signext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: li 4, 0
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: oris 3, 4, 65535
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; NO_ISEL-NEXT: ori 3, 3, 65535
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; NO_ISEL-NEXT: bc 12, 1, .LBB8_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB8_1:
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; NO_ISEL-NEXT: addi 3, 0, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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; select Cond, -1, 0 --> sext (Cond)
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define i32 @select_neg1_or_0(i1 %cond) {
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; ISEL-LABEL: select_neg1_or_0:
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; ISEL: # BB#0:
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; ISEL-NEXT: li 4, 0
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: oris 3, 4, 65535
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; ISEL-NEXT: ori 3, 3, 65535
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; ISEL-NEXT: isel 3, 3, 4, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_neg1_or_0:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: li 4, 0
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: oris 3, 4, 65535
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; NO_ISEL-NEXT: ori 3, 3, 65535
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; NO_ISEL-NEXT: bclr 12, 1, 0
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; NO_ISEL-NEXT: # BB#1:
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; NO_ISEL-NEXT: ori 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
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; ISEL-LABEL: select_neg1_or_0_zeroext:
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; ISEL: # BB#0:
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; ISEL-NEXT: li 4, 0
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: oris 3, 4, 65535
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; ISEL-NEXT: ori 3, 3, 65535
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; ISEL-NEXT: isel 3, 3, 4, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_neg1_or_0_zeroext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: li 4, 0
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: oris 3, 4, 65535
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; NO_ISEL-NEXT: ori 3, 3, 65535
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; NO_ISEL-NEXT: bclr 12, 1, 0
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; NO_ISEL-NEXT: # BB#1:
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; NO_ISEL-NEXT: ori 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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define i32 @select_neg1_or_0_signext(i1 signext %cond) {
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; ISEL-LABEL: select_neg1_or_0_signext:
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; ISEL: # BB#0:
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; ISEL-NEXT: li 4, 0
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: oris 3, 4, 65535
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; ISEL-NEXT: ori 3, 3, 65535
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; ISEL-NEXT: isel 3, 3, 4, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_neg1_or_0_signext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: li 4, 0
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: oris 3, 4, 65535
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; NO_ISEL-NEXT: ori 3, 3, 65535
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; NO_ISEL-NEXT: bclr 12, 1, 0
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; NO_ISEL-NEXT: # BB#1:
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; NO_ISEL-NEXT: ori 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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; select Cond, C+1, C --> add (zext Cond), C
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define i32 @select_Cplus1_C(i1 %cond) {
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; ISEL-LABEL: select_Cplus1_C:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 42
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; ISEL-NEXT: li 3, 41
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_Cplus1_C:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 42
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; NO_ISEL-NEXT: li 3, 41
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; NO_ISEL-NEXT: bc 12, 1, .LBB12_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB12_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
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; ISEL-LABEL: select_Cplus1_C_zeroext:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 42
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; ISEL-NEXT: li 3, 41
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_Cplus1_C_zeroext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 42
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; NO_ISEL-NEXT: li 3, 41
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; NO_ISEL-NEXT: bc 12, 1, .LBB13_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB13_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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define i32 @select_Cplus1_C_signext(i1 signext %cond) {
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; ISEL-LABEL: select_Cplus1_C_signext:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 42
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; ISEL-NEXT: li 3, 41
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_Cplus1_C_signext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 42
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; NO_ISEL-NEXT: li 3, 41
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; NO_ISEL-NEXT: bc 12, 1, .LBB14_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB14_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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; select Cond, C, C+1 --> add (sext Cond), C
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define i32 @select_C_Cplus1(i1 %cond) {
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; ISEL-LABEL: select_C_Cplus1:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 41
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; ISEL-NEXT: li 3, 42
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_C_Cplus1:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 41
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; NO_ISEL-NEXT: li 3, 42
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; NO_ISEL-NEXT: bc 12, 1, .LBB15_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB15_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
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; ISEL-LABEL: select_C_Cplus1_zeroext:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 41
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; ISEL-NEXT: li 3, 42
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_C_Cplus1_zeroext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 41
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; NO_ISEL-NEXT: li 3, 42
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; NO_ISEL-NEXT: bc 12, 1, .LBB16_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB16_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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define i32 @select_C_Cplus1_signext(i1 signext %cond) {
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; ISEL-LABEL: select_C_Cplus1_signext:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 41
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; ISEL-NEXT: li 3, 42
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; ISEL-NEXT: isel 3, 4, 3, 1
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; ISEL-NEXT: blr
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;
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; NO_ISEL-LABEL: select_C_Cplus1_signext:
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; NO_ISEL: # BB#0:
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; NO_ISEL-NEXT: andi. 3, 3, 1
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; NO_ISEL-NEXT: li 4, 41
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; NO_ISEL-NEXT: li 3, 42
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; NO_ISEL-NEXT: bc 12, 1, .LBB17_1
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; NO_ISEL-NEXT: blr
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; NO_ISEL-NEXT: .LBB17_1:
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; NO_ISEL-NEXT: addi 3, 4, 0
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; NO_ISEL-NEXT: blr
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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; In general, select of 2 constants could be:
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; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
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define i32 @select_C1_C2(i1 %cond) {
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; ISEL-LABEL: select_C1_C2:
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; ISEL: # BB#0:
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; ISEL-NEXT: andi. 3, 3, 1
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; ISEL-NEXT: li 4, 421
|
|
; ISEL-NEXT: li 3, 42
|
|
; ISEL-NEXT: isel 3, 4, 3, 1
|
|
; ISEL-NEXT: blr
|
|
;
|
|
; NO_ISEL-LABEL: select_C1_C2:
|
|
; NO_ISEL: # BB#0:
|
|
; NO_ISEL-NEXT: andi. 3, 3, 1
|
|
; NO_ISEL-NEXT: li 4, 421
|
|
; NO_ISEL-NEXT: li 3, 42
|
|
; NO_ISEL-NEXT: bc 12, 1, .LBB18_1
|
|
; NO_ISEL-NEXT: blr
|
|
; NO_ISEL-NEXT: .LBB18_1:
|
|
; NO_ISEL-NEXT: addi 3, 4, 0
|
|
; NO_ISEL-NEXT: blr
|
|
%sel = select i1 %cond, i32 421, i32 42
|
|
ret i32 %sel
|
|
}
|
|
|
|
define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
|
|
; ISEL-LABEL: select_C1_C2_zeroext:
|
|
; ISEL: # BB#0:
|
|
; ISEL-NEXT: andi. 3, 3, 1
|
|
; ISEL-NEXT: li 4, 421
|
|
; ISEL-NEXT: li 3, 42
|
|
; ISEL-NEXT: isel 3, 4, 3, 1
|
|
; ISEL-NEXT: blr
|
|
;
|
|
; NO_ISEL-LABEL: select_C1_C2_zeroext:
|
|
; NO_ISEL: # BB#0:
|
|
; NO_ISEL-NEXT: andi. 3, 3, 1
|
|
; NO_ISEL-NEXT: li 4, 421
|
|
; NO_ISEL-NEXT: li 3, 42
|
|
; NO_ISEL-NEXT: bc 12, 1, .LBB19_1
|
|
; NO_ISEL-NEXT: blr
|
|
; NO_ISEL-NEXT: .LBB19_1:
|
|
; NO_ISEL-NEXT: addi 3, 4, 0
|
|
; NO_ISEL-NEXT: blr
|
|
%sel = select i1 %cond, i32 421, i32 42
|
|
ret i32 %sel
|
|
}
|
|
|
|
define i32 @select_C1_C2_signext(i1 signext %cond) {
|
|
; ISEL-LABEL: select_C1_C2_signext:
|
|
; ISEL: # BB#0:
|
|
; ISEL-NEXT: andi. 3, 3, 1
|
|
; ISEL-NEXT: li 4, 421
|
|
; ISEL-NEXT: li 3, 42
|
|
; ISEL-NEXT: isel 3, 4, 3, 1
|
|
; ISEL-NEXT: blr
|
|
;
|
|
; NO_ISEL-LABEL: select_C1_C2_signext:
|
|
; NO_ISEL: # BB#0:
|
|
; NO_ISEL-NEXT: andi. 3, 3, 1
|
|
; NO_ISEL-NEXT: li 4, 421
|
|
; NO_ISEL-NEXT: li 3, 42
|
|
; NO_ISEL-NEXT: bc 12, 1, .LBB20_1
|
|
; NO_ISEL-NEXT: blr
|
|
; NO_ISEL-NEXT: .LBB20_1:
|
|
; NO_ISEL-NEXT: addi 3, 4, 0
|
|
; NO_ISEL-NEXT: blr
|
|
%sel = select i1 %cond, i32 421, i32 42
|
|
ret i32 %sel
|
|
}
|
|
|